公开(公告)号：US07920405B2

公开(公告)日：2011-04-05

申请号：US11957756

申请日：2007-12-17

申请人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

发明人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： G11C13/0064 ,  B82Y10/00 ,  G11C11/15 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

摘要： A non-volatile memory device includes a memory cell array including a memory cell array having word lines, bit lines, and non-volatile memory cells, each non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line. The variable resistive material has a resistance level that varies according to data to be stored. A selection circuit selects at least one non-volatile memory cell in which data will be written. An adaptive write circuit/method supplies a write bias to the selected non-volatile memory cell through the bit line connected to the selected non-volatile memory cell to write data in the selected non-volatile memory cell and varies (e.g., increases) the write bias until the resistance level of the selected non-volatile memory cell varies.

摘要翻译： 非易失性存储器件包括存储单元阵列，其包括具有字线，位线和非易失性存储器单元的存储单元阵列，每个非易失性存储单元具有可变电阻材料和连接在相应字之间的存取元件 线和相应的位线。 可变电阻材料具有根据要存储的数据而变化的电阻电平。 选择电路选择要写入数据的至少一个非易失性存储单元。 自适应写入电路/方法通过连接到所选择的非易失性存储器单元的位线向所选择的非易失性存储器单元提供写入偏置，以将数据写入所选择的非易失性存储单元中并且改变（例如，增加） 写入偏置，直到所选择的非易失性存储单元的电阻水平变化。

公开(公告)号：US07869256B2

公开(公告)日：2011-01-11

申请号：US11957812

申请日：2007-12-17

申请人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00 ,  G11C11/14

CPC分类号： G11C13/00 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/009

摘要： A non-volatile memory device is employed in which data values are determined by the polarities at both ends of a cell, The non-volatile memory device includes a first decoder which decodes a plurality of predetermined bit values of a row address into a first address and is disposed in a row direction of a memory cell array; a second decoder which decodes the other bit values of the row address into a second address and is disposed in a column direction of the memory cell array; and a driver which applies bias voltages to a word line which corresponds to the first address or the second address in accordance with the data values. By including first and second decoders and decoding a row address in two steps, a bi-directional RRAM according to the present invention can perform addressing at high speeds while reducing chip size.

摘要翻译： 使用非易失性存储器件，其中数据值由单元两端的极性确定。非易失性存储器件包括将行地址的多个预定位值解码为第一地址的第一解码器 并且设置在存储单元阵列的行方向上; 第二解码器，其将所述行地址的其他位值解码为第二地址，并且被布置在所述存储单元阵列的列方向上; 以及根据数据值对与第一地址或第二地址对应的字线施加偏置电压的驱动器。 通过包括第一和第二解码器并以两个步骤对行地址进行解码，根据本发明的双向RRAM可以在降低芯片尺寸的同时以高速执行寻址。

公开(公告)号：US20100320433A1

公开(公告)日：2010-12-23

申请号：US12872876

申请日：2010-08-31

申请人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： G11C5/063 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  Y10S977/754

摘要： A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

摘要翻译： 一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个 分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字 形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线 形成在全局位线上，均匀分离，并沿第一方向延伸。

公开(公告)号：US07817465B2

公开(公告)日：2010-10-19

申请号：US12453420

申请日：2009-05-11

申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

摘要： A phase change random access (PRAM) memory may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

摘要翻译： 相位随机存取（PRAM）存储器可以包括具有多个相变存储器单元的存储单元阵列和包括补偿单元和读出放大器的数据读取电路，该补偿单元被配置为向感测节点提供补偿 电流以补偿由流过多个相变存储器单元之一的电流引起的感测节点的电平的降低，以及被配置为将感测节点的电平与参考电平进行比较并输出结果的读出放大器 的比较。

公开(公告)号：US20100118601A1

公开(公告)日：2010-05-13

申请号：US12690999

申请日：2010-01-21

申请人： Mu-hui PARK ,  Beak-hyung CHO ,  Hyung-rok OH

发明人： Mu-hui PARK ,  Beak-hyung CHO ,  Hyung-rok OH

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

摘要： In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.

摘要翻译： 在相变随机存取存储器（PRAM）装置中，通过将设置的脉冲施加到失败的PRAM单元来执行写入操作。 设置脉冲包括从第一电流幅度顺序地减小到第二电流幅度的多个级。 第一电流幅度或第二电流幅度从一个写入环路变化到另一个写入环路。

公开(公告)号：US20100090213A1

公开(公告)日：2010-04-15

申请号：US12638599

申请日：2009-12-15

申请人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

发明人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Hyung-Rok Oh

IPC分类号： H01L29/18

CPC分类号： G11C17/16 ,  G11C13/0004 ,  G11C17/165

摘要： A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.

摘要翻译： 提供了一种编程一次性可编程器件的方法。 设置在基板中的开关装置导通，并且将编程电流施加到与开关装置电连接的保险丝，从而切断保险丝。 保险丝包括电连接到开关装置的第一电极，与第一电极间隔开的第二电极和设置在第一和第二电极之间的硫族化物图案。 还公开了相关的一次性可编程器件，相变存储器件和电子系统。

公开(公告)号：US07672156B2

公开(公告)日：2010-03-02

申请号：US11850125

申请日：2007-09-05

申请人： Mu-hui Park ,  Beak-hyung Cho ,  Hyung-rok Oh

发明人： Mu-hui Park ,  Beak-hyung Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

摘要： In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.

摘要翻译： 在相变随机存取存储器（PRAM）装置中，通过将设置的脉冲施加到失败的PRAM单元来执行写入操作。 设置脉冲包括从第一电流幅度顺序地减小到第二电流幅度的多个级。 第一电流幅度或第二电流幅度从一个写入环路变化到另一个写入环路。

公开(公告)号：US07586776B2

公开(公告)日：2009-09-08

申请号：US11945420

申请日：2007-11-27

申请人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

发明人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/79

摘要： There is provided a resistive memory device, the device including: a plurality of word lines and a plurality of bit lines arranged such that the word lines intersect the bit lines; a plurality of resistive memory cells each having a variable resistive material coupled between the corresponding word line and the corresponding bit line and an access element; selecting circuits selecting one of the plurality of resistive memory cells; and a filament-forming circuit supplying a filament-forming voltage to the selected resistive memory cell through the bit line coupled to the selected resistive memory cell while increasing the filament-forming voltage from a predetermined voltage level until filaments having a predetermined thickness are formed in the variable resistive material of the selected resistive memory cell.

摘要翻译： 提供了一种电阻式存储器件，该器件包括：多个字线和多个位线，其布置成使得字线与位线相交; 每个具有耦合在对应的字线和对应的位线之间的可变电阻材料的电阻性存储单元和一个存取元件; 选择所述多个电阻性存储单元之一的选择电路; 以及丝线形成电路，其通过耦合到所选择的电阻性存储单元的位线向所选择的电阻性存储单元提供丝状形成电压，同时从预定电压电平增加灯丝形成电压，直到形成具有预定厚度的灯丝 所选择的电阻性存储单元的可变电阻材料。

公开(公告)号：US07542356B2

公开(公告)日：2009-06-02

申请号：US11790146

申请日：2007-04-24

申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

IPC分类号： G11C7/06

CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。

公开(公告)号：US20090059658A1

公开(公告)日：2009-03-05

申请号：US11949299

申请日：2007-12-03

申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

摘要翻译： 一种装置，非易失性存储装置和非易失性存储器系统包括易失性可变电阻存储器（VRM）单元阵列和具有脉冲选择电路，电流控制电路和电流驱动电路的写入驱动器电路。 电流控制电路接收偏置电压，当数据处于第一电平时，在复位脉冲的使能持续时间期间以第二电平输出控制信号，并且在该组的使能持续时间期间输出处于第一电平的控制信号 数据处于第二级时的脉冲。 当前驱动电路在复位脉冲或设定脉冲的使能期间内向相变存储器阵列输出写入电流。 写入驱动器电路可以根据数据的逻辑电平选择复位脉冲或设置脉冲，并根据复位脉冲或设定脉冲控制施加到相变存储器阵列的电流电平。