公开(公告)号：US20110156240A1

公开(公告)日：2011-06-30

申请号：US12651362

申请日：2009-12-31

Applicant: Jing-En Luan ,  Kim-Yong Goh

Inventor： Jing-En Luan ,  Kim-Yong Goh

IPC: H01L23/488 ,  H01L21/78 ,  H01L21/60

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/03 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A fan-out wafer level package includes a semiconductor die with contact pads positioned on a top surface. A fan-in redistribution layer positioned over the die includes contact pads in electrical communication with the first contact pads of the die. A buffer layer positioned over the fan-in layer includes a plurality of vias, in electrical contact with the contact pads of the fan-in layer. A fan-in redistribution layer is positioned over the buffer layer and includes contact pads on a surface opposite the buffer layer, in electrical communication with the vias. The semiconductor die, fan-in layer, and buffer layer are encapsulated in a molding com-pound layer. Solder contacts, for electrically connecting the semiconductor device to a electronic circuit board, are positioned on contact pads of the fan-out layer. The buffer layer has a substantial thickness, to reduce and distribute shear stresses resulting from thermal mismatch of coefficients of thermal expansion of the semiconductor die and a circuit board.

Abstract translation: 扇形晶片级封装包括具有位于顶表面上的接触焊盘的半导体管芯。 位于管芯上方的扇形重分布层包括与管芯的第一接触垫电连通的接触焊盘。 位于扇入层之上的缓冲层包括与扇入层的接触垫电接触的多个通孔。 风扇再分配层位于缓冲层上方，并且包括与通孔相通的与缓冲层相对的表面上的接触焊盘。 将半导体管芯，扇入层和缓冲层封装在成型层中。 用于将半导体器件电连接到电子电路板的焊接触点位于扇出层的接触焊盘上。 缓冲层具有相当大的厚度，以减少和分配由半导体管芯和电路板的热膨胀系数的热失配导致的剪切应力。

公开(公告)号：US07956475B2

公开(公告)日：2011-06-07

申请号：US12336273

申请日：2008-12-16

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/28

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/49816 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A ball grid array (BGA) package includes a substrate layer having first and second sides. A semiconductor chip is attached to the first side of the substrate layer by a dielectric adhesive layer. A plurality of solder balls are attached to the second side of the substrate layer. The solder balls may be set out by rows and columns. A plurality of wires electrically connect the semiconductor chip to the solder balls. A layer of encapsulating compound is deposited over the semiconductor chip. A step cavity of a selected depth and shape is formed in the layer of encapsulating compound at or near the edge or periphery of the layer of encapsulating compound. The step cavity is separated from the solder balls by the substrate layer but spans over a plurality of selected solder balls.

Abstract translation: 球栅阵列（BGA）封装包括具有第一侧和第二侧的衬底层。 半导体芯片通过介电粘合剂层附接到基板层的第一侧。 多个焊球附着在基板层的第二面上。 焊球可以由行和列排列。 多个电线将半导体芯片电连接到焊球。 一层封装化合物沉积在半导体芯片上。 在密封化合物层的边缘或周边处或附近，在封装化合物层中形成所选择的深度和形状的台阶腔。 阶跃腔通过衬底层与焊球分离，但跨越多个选定的焊球。

公开(公告)号：US07919361B2

公开(公告)日：2011-04-05

申请号：US12800639

申请日：2010-05-19

Applicant: Kum-weng Loo ,  Chek-lim Kho ,  Jing-en Luan

Inventor： Kum-weng Loo ,  Chek-lim Kho ,  Jing-en Luan

IPC: H01L21/56 ,  H01L21/60

CPC classification number: H01L21/565 ,  H01L23/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

Abstract translation: 本公开提供了一种非常薄的半导体封装，其包括具有管芯附接焊盘和多个引线端子的引线框架，附接到管芯附接焊盘并且通过接合线电连接到引线端子的管芯，位置构件设置在 模具和/或管芯附接垫，以及将引线框，模具和位置构件封装在一起以形成半导体封装的成型材料。 用于制造非常薄的半导体封装的方法包括在引线框的管芯安装焊盘的一侧上设置第一位置构件，将管芯附接到管芯附接衬垫的相对侧上，可选地将第二位置构件设置在顶部 的模具，将管芯电连接到引线框架的引线端子，并将引线框架，模具和位置构件封装在一起以形成非常薄的半导体封装。

公开(公告)号：US20100327421A1

公开(公告)日：2010-12-30

申请号：US12495515

申请日：2009-06-30

Applicant: Jing-En Luan

Inventor： Jing-En Luan

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/3107 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/4899 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A protective structure is provided on a substrate to which a semiconductor die is attached. The protective structure surrounds the die and reduces the thermo-mechanical stresses to which the die is subject. The die is protected against cracking, warping, and delamination.

Abstract translation: 在安装有半导体管芯的基板上设置保护结构。 保护结构围绕模具并降低模具所受到的热机械应力。 该模具可防止开裂，翘曲和分层。