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152 条记录 (耗时 0.028 秒)

    SYSTEM OF FUNCTIONAL ELECTRICAL STIMULATION
    31.
    发明申请
    SYSTEM OF FUNCTIONAL ELECTRICAL STIMULATION 有权
    功能电刺激系统

    公开(公告)号：US20130231724A1

    公开(公告)日：2013-09-05

    申请号：US13806952

    申请日：2011-06-28

    申请人： Zengguang Hou ,  Min Tan ,  Yixiong Chen ,  Pengfeng Li ,  Hongbo Wang ,  Long Cheng ,  Guoqing Hu ,  Qingling Li ,  Feng Zhang ,  Jin Hu ,  Xinchao Zhang ,  Yi Hong ,  Junwei Zhang ,  Jinzhu Bai ,  Zhen Lv

    发明人： Zengguang Hou ,  Min Tan ,  Yixiong Chen ,  Pengfeng Li ,  Hongbo Wang ,  Long Cheng ,  Guoqing Hu ,  Qingling Li ,  Feng Zhang ,  Jin Hu ,  Xinchao Zhang ,  Yi Hong ,  Junwei Zhang ,  Jinzhu Bai ,  Zhen Lv

    IPC分类号： A61N1/08

    CPC分类号： A61N1/08 ,  A61N1/36 ,  A61N1/36003

    摘要： The present invention discloses a functional electrical stimulation system comprising a primary power, a boost module, an energy storage section, an output control relay, an automatic discharge circuit, a foot/hand controlled switch, a current detection chip and a current limiting fuse. The boost module comprises n DC chopper circuits connected in series, and outputs a high voltage of 100-200V. According to an enable signal and a current detection signal, the output control relay disables/enables the DC boost module. The automatic discharge circuit discharges capacitance of the energy storage section automatically when the relay turns off the power input. The Foot/hand controlled switch, the current detection chip and the current limiting fuse form a triple accident protection circuit. The functional electrical stimulation system maximizes the intensity of electrical stimulation within the range that the human body can withstand. Meanwhile, it provides multiple security protection mechanisms and enhanced reliability to avoid danger during the use.

    摘要翻译： 本发明公开了一种功能电刺激系统，其包括主电源，升压模块，能量存储部，输出控制继电器，自动放电电路，脚/手控开关，电流检测芯片和限流熔断器。 升压模块包括串联连接的n个DC斩波电路，并输出100-200V的高电压。 根据使能信号和电流检测信号，输出控制继电器禁止/使能直流升压模块。 当继电器关闭电源输入时，自动放电电路自动放电储能部分的电容。 脚/手控开关，电流检测芯片和限流熔断器构成三重事故保护电路。 功能性电刺激系统使人体能承受的范围内的电刺激强度最大化。 同时，它提供多种安全保护机制和增强的可靠性，以避免使用过程中的危险。

    Methods and Compositions for Generation of Induced Pluripotent Stem Cells By RNAA
    32.
    发明申请
    Methods and Compositions for Generation of Induced Pluripotent Stem Cells By RNAA 审中-公开
    通过RNAA产生诱导多能干细胞的方法和组合

    公开(公告)号：US20130210146A1

    公开(公告)日：2013-08-15

    申请号：US13817091

    申请日：2011-08-24

    申请人： Long-Cheng Li

    发明人： Long-Cheng Li

    IPC分类号： C12N5/071

    CPC分类号： C12N5/0696 ,  C12N15/111 ,  C12N2310/13 ,  C12N2501/603 ,  C12N2501/604 ,  C12N2501/605 ,  C12N2501/606

    摘要： The present disclosure provides methods for inducing somatic cells to form induced pluripotent stem (iPS) cells. The method includes introducing a small activating RNA (saRNA) molecule into the somatic cell, where the saRNA molecule increases transcription of a transcription factor that induces the formation of induced pluripotent stem cells. The present disclosure also provides compositions and kits comprising a saRNA molecule that increases transcription of a transcription factor that induces the formation of induced pluripotent stem cells. The present disclosure provides iPS cells comprising at least one exogenous saRNA molecule, where the saRNA molecule increases transcription of a transcription factor that induces the formation of induced pluripotent stem cells.

    摘要翻译： 本公开提供诱导体细胞形成诱导多能干细胞（iPS）细胞的方法。 该方法包括将小活化RNA（saRNA）分子引入体细胞，其中saRNA分子增加诱导诱导的多能干细胞形成的转录因子的转录。 本公开还提供了包含增加诱导诱导的多能干细胞形成的转录因子的转录的saRNA分子的组合物和试剂盒。 本公开提供包含至少一种外源性saRNA分子的iPS细胞，其中所述saRNA分子增加诱导诱导的多能干细胞形成的转录因子的转录。

    Semiconductor device and method of fabricating same
    33.
    发明授权
    Semiconductor device and method of fabricating same 有权
    半导体装置及其制造方法

    公开(公告)号：US08461629B2

    公开(公告)日：2013-06-11

    申请号：US13178755

    申请日：2011-07-08

    申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

    摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

    摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

    E-fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit
    34.
    发明申请
    E-fuse Structure Design in Electrical Programmable Redundancy for Embedded Memory Circuit 有权
    嵌入式存储器电路的电可编程冗余中的电熔丝结构设计

    公开(公告)号：US20120196434A1

    公开(公告)日：2012-08-02

    申请号：US13443550

    申请日：2012-04-10

    申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

    发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

    IPC分类号： H01L21/02

    CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

    摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

    Method and system for optimizing web page images
    36.
    发明授权
    Method and system for optimizing web page images 有权
    用于优化网页图像的方法和系统

    公开(公告)号：US08111944B2

    公开(公告)日：2012-02-07

    申请号：US11956655

    申请日：2007-12-14

    申请人： Long Cheng ,  Xing Fang ,  Sheng Lu ,  Qing Bo Wang ,  Meng Ye

    发明人： Long Cheng ,  Xing Fang ,  Sheng Lu ,  Qing Bo Wang ,  Meng Ye

    IPC分类号： G06K9/36

    CPC分类号： G06F17/30905

    摘要： In computer multimedia technology, a system, method and computer program product for optimizing images and transmission of images of a web-page transmitted over the Internet and furthermore, optimizing images of a web page on a network server. The method includes detecting the images in the web page to determine the relationship among the images; in response to the determination of the relationship among the images, combining two or more related images into a combinational image; and updating the web page to replace references to the related images with a reference to the combinational image. By optimizing web page images, the server's work required for handling heavy amount of HTTP requests in transmitting the web page images is decreased and the bandwidth requirement for transmitting the web page images is reduced. The quality of the original image is not lowered. And there is no need to make any change to the operation at the client side.

    摘要翻译： 在计算机多媒体技术中，一种用于优化通过因特网传输的网页的图像和图像传输的系统，方法和计算机程序产品，此外，优化网络服务器上的网页的图像。 该方法包括检测网页中的图像以确定图像之间的关系; 响应于确定图像之间的关系，将两个或更多个相关图像组合成组合图像; 并且通过参考组合图像来更新网页以替代对相关图像的引用。 通过优化网页图像，服务器在传输网页图像时处理大量HTTP请求所需的工作减少，并减少了传送网页图像的带宽需求。 原始图像的质量不会降低。 而客户端的操作无需改动。

    Semiconductor device with both I/O and core components and method of fabricating same
    37.
    发明授权
    Semiconductor device with both I/O and core components and method of fabricating same 有权
    具有I / O和核心部件的半导体器件及其制造方法

    公开(公告)号：US07998830B2

    公开(公告)日：2011-08-16

    申请号：US12961167

    申请日：2010-12-06

    申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L21/76

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

    摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

    摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

    Method and apparatus for semiconductor device with improved source/drain junctions
    39.
    发明授权
    Method and apparatus for semiconductor device with improved source/drain junctions 有权
    具有改善的源极/漏极结的半导体器件的方法和装置

    公开(公告)号：US07868386B2

    公开(公告)日：2011-01-11

    申请号：US12058997

    申请日：2008-03-31

    申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

    发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

    IPC分类号： H01L23/58 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

    摘要： A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

    摘要翻译： 公开了一种具有改善的源极/漏极结的半导体器件和用于制造该器件的方法。 优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域 形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。 在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度与45度之间。 另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。