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    Circuit arrangement with at least four transistors, and method for the manufacture thereof
    31.
    发明授权
    Circuit arrangement with at least four transistors, and method for the manufacture thereof 有权
    具有至少四个晶体管的电路布置及其制造方法

    公开(公告)号：US6060911A

    公开(公告)日：2000-05-09

    申请号：US138160

    申请日：1998-08-21

    Applicant: Thomas Schulz ,  Thomas Aeugle ,  Wolfgang Roesner ,  Lothar Risch

    Inventor： Thomas Schulz ,  Thomas Aeugle ,  Wolfgang Roesner ,  Lothar Risch

    IPC: G11C16/04 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H03K19/094 ,  H01L29/76

    CPC classification number: H01L27/092 ,  H01L21/823885

    Abstract: In the circuit arrangement two of the four vertical transistors are complementary to the remaining two transistors. Two of the transistors are respectively arranged at the same level. For this purpose, layer structures (St1, St2, St3, St4) are structured that respectively have at least a channel layer and a source/drain region of one of the transistors. All the layer structures (St1, St2, St3, St4) can be produced from a layer sequence with only four layers. In order to avoid leakage currents due to a parasitic bipolar transistor, the layer structures (St1, St2, St3, St4) can be realized very thinly, using spacer-type masks. Electrical connections between parts of the four transistors can take place via layers of the layer sequence. The contacting to the output voltage terminal can take place via a step that is formed by two layers of the layer sequence.

    Abstract translation: 在电路布置中，四个垂直晶体管中的两个与剩余的两个晶体管互补。 两个晶体管分别布置在相同的电平上。 为此，层结构（St1，St2，St3，St4）被构造成分别具有至少一个晶体管的沟道层和源极/漏极区域。 所有的层结构（St1，St2，St3，St4）可以仅由四层制成。 为了避免由寄生双极型晶体管引起的漏电流，使用间隔型掩模，可以非常薄地实现层结构（St1，St2，St3，St4）。 四个晶体管的部分之间的电连接可以通过层序列的层进行。 与输出电压端子的接触可以通过由层序列的两层形成的步骤进行。

    Electrically programmable memory cell arrangement and method for its manufacture
    33.
    发明授权
    Electrically programmable memory cell arrangement and method for its manufacture 失效
    电可编程存储单元布置及其制造方法

    公开(公告)号：US5959328A

    公开(公告)日：1999-09-28

    申请号：US779446

    申请日：1997-01-07

    Applicant: Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann ,  Hans Reisinger

    Inventor： Wolfgang Krautschneider ,  Lothar Risch ,  Franz Hofmann ,  Hans Reisinger

    IPC: H01L21/8247 ,  H01L21/8246 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: An electrically programmable memory cell arrangement has a plurality of individual memory cells that respectively has an MOS transistor with a gate dielectric with traps, and which are arranged in rows that run in parallel. Adjacent rows thereby respectively run in alternating fashion on the bottom of the longitudinal trenches (5) and between adjacent longitudinal trenches (5) and are insulated against one another. The memory cell arrangement can be manufactured by means of self-adjusting process steps with a surface requirement per memory cell of 2 F.sup.2 (F: minimum structural size).

    Abstract translation: 电可编程存储单元布置具有多个单独的存储单元，它们分别具有带栅极电介质的MOS晶体管，并具有陷阱，并且它们排列成并行的行。 因此，相邻的行分别以纵向沟槽（5）的底部和相邻的纵向沟槽（5）之间交替地延伸并彼此绝缘。 可以通过自调整工艺步骤制造存储单元布置，每个存储单元的表面要求为2×2（F：最小结构尺寸）。

    Process of making a dram cell arrangement
    35.
    发明授权
    Process of making a dram cell arrangement 失效
    制作电视剧排列的过程

    公开(公告)号：US5817552A

    公开(公告)日：1998-10-06

    申请号：US635526

    申请日：1996-04-22

    Applicant: Wolfgang Roesner ,  Lothar Risch ,  Franz Hofman ,  Wolfgang Krautschneider

    Inventor： Wolfgang Roesner ,  Lothar Risch ,  Franz Hofman ,  Wolfgang Krautschneider

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10876 ,  H01L27/10823

    Abstract: For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of which is connected to a buried bit line. The DRAM cell arrangement can be produced with a storage-cell area of 4F.sup.2 by using only two masks, F being the minimum producible structure size in the respective technology.

    Abstract translation: 对于每个存储单元，DRAM单元布置具有垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储器节点，其存储电容器的沟道区域被栅电极环形地包围，并且第二源极 漏极区连接到埋地位线。 可以通过仅使用两个掩模来制造具有4F2的存储单元面积的DRAM单元布置，F是相应技术中的最小可生产结构尺寸。

    DRAM cell arrangement and method for its manufacture
    36.
    发明授权
    DRAM cell arrangement and method for its manufacture 失效
    DRAM单元布置及其制造方法

    公开(公告)号：US5736761A

    公开(公告)日：1998-04-07

    申请号：US645503

    申请日：1996-05-14

    Applicant: Lothar Risch ,  Franz Hofmann ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    Inventor： Lothar Risch ,  Franz Hofmann ,  Wolfgang Roesner ,  Wolfgang Krautschneider

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: H01L27/10876 ,  H01L27/10823

    Abstract: The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.

    Abstract translation: DRAM单元布置对每个存储单元具有一个垂直MOS晶体管，其第一源极/漏极区域邻接沟槽位线（5），其栅极电极（13）与沟槽字线连接，并且其第二源极/漏极区域（3）邻接 基板主表面（1）。 至少在第二源极/漏极区域上布置有特别是铁电体或者顺电层的电容器电介质（16），并且电容器板（17）布置在电介质上，使得第二源极/漏极区域 3）另外作为存储器节点。 可以利用4F2的存储单元表面来制造DRAM单元布置。

    Method for manufacturing an integrated circuit having at least one MOS transistor
    37.
    发明授权
    Method for manufacturing an integrated circuit having at least one MOS transistor 失效
    一种具有至少一个MOS晶体管的集成电路的制造方法

    公开(公告)号：US5443992A

    公开(公告)日：1995-08-22

    申请号：US332733

    申请日：1994-11-01

    Applicant: Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

    Inventor： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

    IPC: H01L21/8238 ,  H01L21/336 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L21/265 ,  H01L21/20 ,  H01L21/302 ,  H01L21/76

    CPC classification number: H01L29/66666 ,  H01L27/092 ,  H01L29/7827 ,  H01L29/42368

    Abstract: An insulating layer is grown on a principal face of a substrate that comprises a source terminal region. A first opening wherein the surface of the source terminal region is partially uncovered is provided in the insulating layer. A vertical layer sequence that comprises at least a channel region and a drain region for the MOS transistor is produced in the first opening by epitaxial growth of semiconductor material within situ doping. A second opening that is at least of a depth corresponding to the sum of the thicknesses of drain region and channel region is produced in the layer structure, a gate dielectric is applied on the surface thereof and a gate-electrode is applied on said gate dielectric.

    Abstract translation: 在包括源极端子区域的基板的主面上生长绝缘层。 在绝缘层中设置有源极端子区域的表面部分未覆盖的第一开口。 在第一开口中通过外延生长半导体材料在原位掺杂中产生至少包括MOS晶体管的沟道区和漏极区的垂直层序列。 在层结构中产生至少具有与漏极区域和沟道区域的厚度之和相对应的深度的第二开口，在其表面上施加栅极电介质，并且在所述栅极电介质上施加栅极电极 。

    Process for making a contact betwen a capacitor electrode disposed in a trench and an MOS transistor source/drain region disposed outside the trench
    38.
    发明授权
    Process for making a contact betwen a capacitor electrode disposed in a trench and an MOS transistor source/drain region disposed outside the trench 失效
    在设置在沟槽中的电容器电极和设置在沟槽外部的MOS晶体管源极/漏极区之间进行接触的工艺

    公开(公告)号：US5432115A

    公开(公告)日：1995-07-11

    申请号：US284502

    申请日：1994-08-04

    Applicant: Wolfgang Rosner ,  Franz Hofmann ,  Lothar Risch

    Inventor： Wolfgang Rosner ,  Franz Hofmann ,  Lothar Risch

    IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC classification number: H01L27/10861 ,  H01L27/10829

    Abstract: To make a contact between a capacitor electrode (13) disposed in a trench (11) and an MOS transistor source/drain region disposed outside the trench, a shallow etching is carried out in a self-aligned manner with respect to a field-oxide region insulating the MOS transistor by producing the trench (11) in a substrate (1). After forming an Si.sub.3 N.sub.4 spacer (10) at the edge (8), laid bare during the etching, of the substrate (1) the part laid bare of the field-oxide region (2) is first removed with the aid of a mask and the trench (11) is completed in a further etching. The contact is produced after the formation of an SiO.sub.2 layer (12) at the surface of the trench (11) after removing the Si.sub.3 N.sub.4 spacer (10) and producing the capacitor electrode (13) at the edge (8), laid bare by removing the Si.sub.3 N.sub.4 spacer (10), of the substrate (1).

    Abstract translation: PCT No.PCT / DE93 / 00078 Sec。 371日期：1994年8月4日 102（e）日期1994年8月4日PCT提交1993年2月1日PCT公布。 出版物WO93 / 16490 日期：1993年8月19日。为了在布置在沟槽（11）中的电容器电极（13）和设置在沟槽外部的MOS晶体管源/漏区之间进行接触，以自对准的方式进行浅蚀刻 相对于通过在衬底（1）中产生沟槽（11）来绝缘MOS晶体管的场氧化物区域。 在蚀刻过程中在边缘（8）处形成Si3N4间隔物（10）之后，在衬底（1）上放置裸露的场氧化物区域（2）的部分首先借助掩模去除， 在另外的蚀刻中完成沟槽（11）。 在除去Si 3 N 4间隔物（10）之后在沟槽（11）的表面形成SiO 2层（12）并在边缘（8）处产生电容器电极（13），在通过去除 （1）的Si 3 N 4间隔物（10）。

    Large scale integrable memory cell with a trench capacitor wherein the trench edge is surrounded by a field oxide region
    39.
    发明授权
    Large scale integrable memory cell with a trench capacitor wherein the trench edge is surrounded by a field oxide region 失效
    具有沟槽电容器的大规模可积分存储单元，其中沟槽边缘被场氧化物区域包围

    公开(公告)号：US4905193A

    公开(公告)日：1990-02-27

    申请号：US372236

    申请日：1989-06-26

    Applicant: Lothar Risch ,  Reinhard Tielert

    Inventor： Lothar Risch ,  Reinhard Tielert

    IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10861 ,  H01L27/10829

    Abstract: A large scale integrable memory cell including a field effect transistor lying at a bit line and further including a storage capacitor which is formed by the wall of a trench and a cooperating electrode. The active region of the storage cell which lies outside the trench is fashioned in the form of a strip. The end face forms one part of the trench edge and the remaining portion of the trench edge is surrounded by a field oxide region.

    Abstract translation: 一种大规模可积分存储单元，包括位于位线处的场效应晶体管，还包括由沟槽壁和配合电极形成的存储电容器。 位于沟槽外部的存储单元的有源区域以条带的形式形成。 端面形成沟槽边缘的一部分，并且沟槽边缘的剩余部分被场氧化物区域包围。

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