公开(公告)号：US5828076A

公开(公告)日：1998-10-27

申请号：US727440

申请日：1996-10-17

申请人： Harald Gossner ,  Ignaz Eisele ,  Lothar Risch ,  Erwin Hammerl

发明人： Harald Gossner ,  Ignaz Eisele ,  Lothar Risch ,  Erwin Hammerl

IPC分类号： H01L29/78 ,  B82B1/00 ,  H01L21/20 ,  H01L21/335 ,  H01L29/06 ,  H01L29/10 ,  H01L29/12 ,  H01L29/423

CPC分类号： H01L29/127 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/78

摘要： In its gate region (10), a silicon MOS technology component has a surface structure (6) having edges and/or vertices at which inversion regions, suitable as quantum wires or quantum dots, are preferentially formed when a gate voltage is applied. The surface structure is preferably formed as a silicon pyramid (6) by local molecular beam epitaxy.

摘要翻译： PCT No.PCT / DE95 / 00448 Sec。 371日期1996年10月17日第 102（e）日期1996年10月17日PCT提交1995年4月4日PCT公布。 WO95 / 28741 PCT出版物 日期1995年10月26日在其栅极区域（10）中，硅MOS技术部件具有具有边缘和/或顶点的表面结构（6），当栅极（10）处优选形成适合作为量子线或量子点的反转区域 施加电压。 表面结构优选通过局部分子束外延形成为硅金字塔（6）。

公开(公告)号：US5516404A

公开(公告)日：1996-05-14

申请号：US275382

申请日：1994-07-15

申请人： Ignaz Eisele ,  Harald Gossner ,  Hermann Baumgaertner ,  Lothar Risch

发明人： Ignaz Eisele ,  Harald Gossner ,  Hermann Baumgaertner ,  Lothar Risch

IPC分类号： H01L21/203 ,  C30B23/02 ,  H01J9/02 ,  H01L21/20 ,  H01L21/28 ,  H01L21/306 ,  H01L29/41

CPC分类号： C30B29/06 ,  C30B23/02 ,  H01J9/025 ,  H01J2201/30426

摘要： A method for manufacturing an electrically conductive tip for field emission cathodes of vacuum electronic components includes forming the tip of doped silicon by molecular beam epitaxy of doped silicon through an opening of a mask and onto a substrate of monocrystalline silicon. The molecular beam epitaxy also produces a doped silicon layer on the surface of the mask.

摘要翻译： 用于制造真空电子部件的场致发射阴极的导电尖端的方法包括通过掩模的开口通过掺杂硅的分子束外延形成掺杂硅的尖端并到单晶硅的衬底上。 分子束外延还在掩模的表面上产生掺杂的硅层。

公开(公告)号：US6067247A

公开(公告)日：2000-05-23

申请号：US47162

申请日：1998-03-23

申请人： Harald Gossner ,  Ignaz Eisele ,  Franz Wittmann ,  Rao Ramgopal

发明人： Harald Gossner ,  Ignaz Eisele ,  Franz Wittmann ,  Rao Ramgopal

IPC分类号： G11C11/412 ,  G11C11/40 ,  G11C16/04 ,  G11C11/41

CPC分类号： G11C11/40

摘要： A three-transistor SRAM memory cell includes a bistable field-effect transistor having a fully depleted floating channel region and a hysteretic gate voltage characteristic curve. The bistable field-effect transistor has a gate to be connected to a first bit line for the purpose of writing to the memory cell and a second channel terminal to be connected to a second bit line for the purpose of reading from the memory cell. The two bit lines can be identical. The connection between the bit lines and the bistable transistor can be effected through first and second respective transistors which are each controlled by a respective word line.

摘要翻译： 三晶体管SRAM存储单元包括具有完全耗尽的浮动沟道区和迟滞栅极电压特性曲线的双稳态场效应晶体管。 双稳态场效应晶体管具有要连接到第一位线的栅极，用于写入存储器单元，以及要连接到第二位线的第二通道端子，用于从存储单元读取。 两条位线可以相同。 位线和双稳态晶体管之间的连接可以通过第一和第二相应的晶体管实现，这些晶体管各自由相应的字线控制。

公开(公告)号：US20140097465A1

公开(公告)日：2014-04-10

申请号：US13646799

申请日：2012-10-08

申请人： Mayank Shrivastava ,  Harald Gossner

发明人： Mayank Shrivastava ,  Harald Gossner

IPC分类号： H01L29/74 ,  H01L21/332

CPC分类号： H01L27/0817 ,  H01L21/845 ,  H01L27/1211

摘要： Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.

摘要翻译： 一些方面涉及设置在半导体衬底上的半导体器件。 该器件包括横向围绕半导体鳍片的基底部分的STI区域。 具有第一导电类型的阳极区域和具有第二导电类型的阴极区域布置在半导体鳍片的上部。 具有第二导电类型的第一掺杂基极区布置在阳极区域下方的翅片的底部。 具有第一导电类型的第二掺杂基区布置在阴极区下方的鳍的底部。 电流控制单元设置在阳极区域和阴极区域之间。 电流控制单元被布置为基于触发信号来选择性地启用和禁止鳍的上部中的电流。 还公开了其它装置和方法。

公开(公告)号：US08643090B2

公开(公告)日：2014-02-04

申请号：US12408839

申请日：2009-03-23

申请人： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

发明人： Mayank Shrivastava ,  Harald Gossner ,  Ramgopal Rao ,  Maryam Shojaei Baghini

IPC分类号： H01L29/66

CPC分类号： H01L29/0653 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

摘要： In various embodiments, a semiconductor device is provided. The semiconductor device may include a first source/drain region, a second source/drain region, an active region electrically coupled between the first source/drain region and the second source/drain region, a trench disposed between the second source/drain region and at least a portion of the active region, a first isolation layer disposed over the bottom and the sidewalls of the trench, electrically conductive material disposed over the isolation layer in the trench, a second isolation layer disposed over the active region, and a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.

摘要翻译： 在各种实施例中，提供半导体器件。 半导体器件可以包括第一源极/漏极区域，第二源极/漏极区域，电耦合在第一源极/漏极区域和第二源极/漏极区域之间的有源区域，设置在第二源极/漏极区域和第二源极/ 所述有源区的至少一部分，设置在所述沟槽的底部和所述侧壁上的第一隔离层，设置在所述沟槽中的所述隔离层上的导电材料，设置在所述有源区上的第二隔离层和栅极区 设置在第二隔离层上。 导电材料可以耦合到电接触。

公开(公告)号：US20130250461A1

公开(公告)日：2013-09-26

申请号：US13429577

申请日：2012-03-26

申请人： Mayank Shrivastava ,  Christian Russ ,  Harald Gossner

发明人： Mayank Shrivastava ,  Christian Russ ,  Harald Gossner

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit from an ESD event. The ESD protection device includes first and second trigger elements. Upon detecting an ESD pulse, the first trigger element provides a first trigger signal having a first pulse length. The second trigger element, upon detecting the ESD pulse, provides a second trigger signal having a second pulse length. The second pulse length is different from the first pulse length. A primary shunt shunts power of the ESD pulse away from the ESD susceptible circuit based on the first trigger signal. A current control element selectively pumps current due to the ESD pulse into a substrate of the primary shunt based on the second trigger signal.

摘要翻译： 一些实施例涉及用于保护电路免受ESD事件的静电放电（ESD）保护装置。 ESD保护装置包括第一和第二触发元件。 在检测到ESD脉冲时，第一触发元件提供具有第一脉冲长度的第一触发信号。 第二触发元件在检测到ESD脉冲时提供具有第二脉冲长度的第二触发信号。 第二脉冲长度与第一脉冲长度不同。 基于第一触发信号，主分流器将ESD脉冲的功率分配离开ESD敏感电路。 电流控制元件基于第二触发信号选择性地将由于ESD脉冲引起的电流泵送到主分流器的衬底中。

公开(公告)号：US08536648B2

公开(公告)日：2013-09-17

申请号：US13020368

申请日：2011-02-03

申请人： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

发明人： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC分类号： H01L29/76

CPC分类号： H01L29/1095 ,  H01L21/26513 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842

摘要： In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

公开(公告)号：US08390970B2

公开(公告)日：2013-03-05

申请号：US12912781

申请日：2010-10-27

申请人： Harald Gossner ,  David Johnsson ,  Wolfgang Soldner

发明人： Harald Gossner ,  David Johnsson ,  Wolfgang Soldner

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： A method and a system for ESD protection are provided. In one embodiment, the system comprises a circuit comprising at least one non-linear element, an application module configured to apply a set of current pulses to the circuit, a determination module configured to determine at least one frequency-dependent and amplitude-dependent transfer function of the circuit based on the set of applied current pulses, a modeling module configured to model at least one frequency-dependent and current-dependent impedance of the at least one non-linear element, and a simulation module to simulate a transmission to the circuit based on the model.

摘要翻译： 提供了ESD保护的方法和系统。 在一个实施例中，系统包括包括至少一个非线性元件的电路，被配置为将一组电流脉冲施加到电路的应用模块，被配置为确定至少一个频率相关和幅度相关的转移 基于所施加的电流脉冲集合的电路的功能，被配置为对所述至少一个非线性元件的至少一个频率相关和依赖于电流的阻抗建模的建模模块，以及模拟模块，用于模拟到 电路基于模型。

公开(公告)号：US08093689B2

公开(公告)日：2012-01-10

申请号：US11772272

申请日：2007-07-02

申请人： Wolfgang Stadler ,  Harald Gossner ,  Reinhold Gaertner

发明人： Wolfgang Stadler ,  Harald Gossner ,  Reinhold Gaertner

IPC分类号： H01L23/58

CPC分类号： H01L23/60 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor sensor device is electrically coupled to an object. An attachment member attaches the semiconductor sensor device to the object. The attachment member comprises a first conductive contact region and a second conductive contact region. An insulating portion is electrically isolates the semiconductor sensor device from the first conductive contact region and second conductive contact region.

摘要翻译： 半导体传感器装置电耦合到物体。 附接构件将半导体传感器装置附接到物体。 附接构件包括第一导电接触区域和第二导电接触区域。 绝缘部分将半导体传感器装置与第一导电接触区域和第二导电接触区域电隔离。

公开(公告)号：US07919816B2

公开(公告)日：2011-04-05

申请号：US11506683

申请日：2006-08-18

申请人： Harald Gossner ,  Christian Russ

发明人： Harald Gossner ,  Christian Russ

IPC分类号： H01L23/62

CPC分类号： H01L27/1211 ,  H01L27/0288 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/8086 ,  H01L2029/7857

摘要： A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.

摘要翻译： 在电路中用作静电放电（ESD）保护元件的栅极控制鳍电阻元件具有鳍状结构，其具有形成在第一和第二连接区域之间的第一连接区域，第二连接区域和沟道区域。 此外，散热片电阻元件具有形成在通道区域的表面的至少一部分上的栅极区域。 栅极区域电耦合到栅极控制装置，栅极控制装置控制施加到栅极区域的电位，使得栅极控制的鳍状电阻元件在电路的第一操作状态期间具有高电阻 并且在第二操作状态期间具有较低的电阻，其特征在于发生ESD事件。