公开(公告)号：US07321154B2

公开(公告)日：2008-01-22

申请号：US11465219

申请日：2006-08-17

申请人： Luigi Colombo ,  James J Chambers ,  Mark R Visokay

发明人： Luigi Colombo ,  James J Chambers ,  Mark R Visokay

IPC分类号： H01L29/76

CPC分类号： H01L21/823842 ,  H01L29/4958

摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

公开(公告)号：US07291890B2

公开(公告)日：2007-11-06

申请号：US11339393

申请日：2006-01-25

申请人： Mark R. Visokay ,  Antonio L. P. Rotondaro ,  Luigi Colombo

发明人： Mark R. Visokay ,  Antonio L. P. Rotondaro ,  Luigi Colombo

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

摘要翻译： 具有高k栅极电介质层和硅或金属栅极的MOSFET结构，与等离子体或离子注入一起对高k栅极介电层进行非晶化处理。

公开(公告)号：US07229873B2

公开(公告)日：2007-06-12

申请号：US11200741

申请日：2005-08-10

申请人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay

发明人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/04 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

摘要翻译： 本发明提供一种形成双功函数金属栅极微电子器件200的方法。 在一个方面，该方法包括形成nMOS和pMOS堆叠栅极结构315a和315b。 nMOS和pMOS堆叠栅极结构315a和315b各自包括栅极电介质205，位于栅极电介质205上方的第一金属层305和位于第一金属层305上方的牺牲栅极层310。 该方法还包括在nMOS或pMOS堆叠栅极结构中的至少一个中去除牺牲栅极层310，从而形成栅极开口825并修改栅极开口825内的第一金属层305以形成具有所需工作的栅电极 功能。

公开(公告)号：US07226826B2

公开(公告)日：2007-06-05

申请号：US10826516

申请日：2004-04-16

申请人： Husam N. Alshareef ,  Mark R. Visokay ,  Antonio Luis Pacheco Rotondaro ,  Luigi Colombo

发明人： Husam N. Alshareef ,  Mark R. Visokay ,  Antonio Luis Pacheco Rotondaro ,  Luigi Colombo

IPC分类号： H01L21/8238

CPC分类号： H01L21/321 ,  H01L21/28079 ,  H01L21/823835 ,  H01L21/823842

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。 半导体器件（100）以及其他可能的元件包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有具有功函数的金属栅电极（135） 第二晶体管（160）位于半导体衬底（110）上并且靠近第一晶体管（120），其中第二晶体管（160）具有具有不同功函数的等离子体改变的金属栅电极（175）。

公开(公告)号：US07119386B2

公开(公告)日：2006-10-10

申请号：US11221103

申请日：2005-09-07

申请人： Mark R. Visokay ,  James J. Chambers

发明人： Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L29/76

CPC分类号： H01L29/7831 ,  H01L29/66484

摘要： The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

摘要翻译： 本发明提供一种利用标准半导体衬底（302）制造三栅晶体管段（300）的系统。 衬底具有沿着其上表面以远侧分开的关系形成的多个隔离区域（304），其限定沟道区域（306）。 形式结构（308）设置在隔离区顶部，并且限定通道区域上的通道体区域（310）。 通道体结构（316）设置在通道主体区域内，并被设计成沿着其上暴露表面的周边提供钝角或边缘（318）。 然后去除形式结构，并执行后续处理。

公开(公告)号：US07067434B2

公开(公告)日：2006-06-27

申请号：US10745449

申请日：2003-12-22

申请人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay

发明人： Luigi Colombo ,  James J. Chambers ,  Mark R. Visokay

IPC分类号： H01L21/302

CPC分类号： H01L21/28194 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31608 ,  H01L21/3185 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  Y10S438/91 ,  Y10S438/954

摘要： The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.

摘要翻译： 本发明涉及在不存在氢的情况下形成晶体管，或者在显着减少量的氢的存在下。 以这种方式，可以利用高k材料在晶体管中形成栅极电介质层，并且便于器件缩放，同时减轻可通过存在氢和/或含氢化合物引入高k材料的缺陷。

公开(公告)号：US06969644B1

公开(公告)日：2005-11-29

申请号：US10930273

申请日：2004-08-31

申请人： Mark R. Visokay ,  James J. Chambers

发明人： Mark R. Visokay ,  James J. Chambers

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7831 ,  H01L29/66484

摘要： The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

摘要翻译： 本发明提供一种利用标准半导体衬底（302）制造三栅晶体管段（300）的系统。 衬底具有沿着其上表面以远侧分开的关系形成的多个隔离区域（304），其限定沟道区域（306）。 形式结构（308）设置在隔离区顶部，并且限定通道区域上的通道体区域（310）。 通道体结构（316）设置在通道主体区域内，并被设计成沿着其上暴露表面的周边提供钝角或边缘（318）。 然后去除形式结构，并执行后续处理。

公开(公告)号：US06797599B2

公开(公告)日：2004-09-28

申请号：US10232124

申请日：2002-08-30

申请人： Mark R. Visokay ,  Antonio L. P. Rotondaro ,  Luigi Colombo

发明人： Mark R. Visokay ,  Antonio L. P. Rotondaro ,  Luigi Colombo

IPC分类号： H01L213205

CPC分类号： H01L21/28185 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/823857 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A MOSFSET structure with high-k gate dielecttrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate material desposition and gate formation.

摘要翻译： 一种具有高k栅极介质的MOSFSET结构，用于在栅极材料沉积和栅极形成之前的栅极介质液体氧化表面处理的硅或金属栅极。

公开(公告)号：US06380080B2

公开(公告)日：2002-04-30

申请号：US09520492

申请日：2000-03-08

申请人： Mark R. Visokay

发明人： Mark R. Visokay

IPC分类号： H01L2144

CPC分类号： C23C16/40 ,  C23C16/16 ,  C23C16/18

摘要： The present invention provides methods for the preparation of ruthenium metal films from liquid ruthenium complexes of the formula (diene)Ru(CO)3, wherein “diene” refers to linear, branched, or cyclic dienes, bicyclic dienes, tricyclic dienes, fluorinated derivatives thereof, combinations thereof, or derivatives thereof additionally containing heteroatoms such as halide, Si, S, Se, P, As, N, or O, in the presence of an oxidizing gas.

公开(公告)号：US6090697A

公开(公告)日：2000-07-18

申请号：US105411

申请日：1998-06-26

申请人： Guoqiang Xing ,  Glenn A. Cerny ,  Mark R. Visokay

发明人： Guoqiang Xing ,  Glenn A. Cerny ,  Mark R. Visokay

IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/4763

CPC分类号： H01L28/55 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76831 ,  H01L21/7687 ,  H01L28/60 ,  H01L21/0332 ,  H01L27/10852

摘要： A high-selectivity via etching process. The process includes the steps of: forming an etchstop layer 840 of a material selected from the group consisting of Ti--Al, Ti--Al--N, Ta--Al, Al--N, Ti--Al/Ti--N, Ti--Al--N/Ti--N, Ta--Al/Ti--N, and Ti--Al/Ti--Al--N; forming a dielectric layer over the etchstop layer; and etching the dielectric layer with a fluorine-bearing etchant.

摘要翻译： 高选择性通过蚀刻工艺。 该方法包括以下步骤：形成选自Ti-Al，Ti-Al-N，Ta-Al，Al-N，Ti-Al / Ti-N，Ti-Al -N / Ti-N，Ta-Al / Ti-N和Ti-Al / Ti-Al-N; 在所述蚀刻阻挡层上形成介电层; 并用含氟蚀刻剂蚀刻介电层。