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29 条记录 (耗时 0.023 秒)

    Dual cap layer in damascene interconnection processes
    2.
    发明授权
    Dual cap layer in damascene interconnection processes 有权
    大马士革互连工艺中的双盖层

    公开(公告)号：US07129162B2

    公开(公告)日：2006-10-31

    申请号：US10429119

    申请日：2003-05-02

    申请人： Hyesook Hong ,  Guoqiang Xing ,  Ping Jiang

    发明人： Hyesook Hong ,  Guoqiang Xing ,  Ping Jiang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76832 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76808

    摘要： Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.

    摘要翻译： 公开了用于形成铜导体（30,130）的镶嵌方法。 根据所公开的方法，在将通孔或沟槽蚀刻到下面的导体（12;）之前，在有机硅酸盐玻璃绝缘层（16; 116,120）上形成双重覆盖层（18,20; 122,124）。 112）。 双盖层包括碳化硅层（18; 124）和氮化硅层（20; 122）。 碳化硅层（18; 124）和氮化硅层（20; 122）可以以相对于彼此的任何顺序沉积。 碳化硅层（18; 124）在蚀刻通过绝缘层（16; 116,120）时保持通孔或沟槽的临界尺寸，而氮化硅层（20; 122）抑制抗蚀剂的失效机理 中毒 该方法适用于单镶嵌工艺，但也可用于双镶嵌铜工艺。

    Hydrogen-free contact etch for ferroelectric capacitor formation
    4.
    发明授权
    Hydrogen-free contact etch for ferroelectric capacitor formation 有权
    用于铁电电容器形成的无氢接触蚀刻

    公开(公告)号：US06485988B2

    公开(公告)日：2002-11-26

    申请号：US09741650

    申请日：2000-12-19

    申请人： Shawming Ma ,  Guoqiang Xing ,  Rahim Kavari ,  Scott R. Summerfelt ,  Tomoyuki Sakoda

    发明人： Shawming Ma ,  Guoqiang Xing ,  Rahim Kavari ,  Scott R. Summerfelt ,  Tomoyuki Sakoda

    IPC分类号： H01L2100

    CPC分类号： H01L21/31122 ,  H01L21/32136 ,  H01L21/76838 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60

    摘要： An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.

    摘要翻译： 本发明的一个实施方案是一种形成导电接触的方法，该导电接触由位于顶部电极下方的底部电极（图4d的304）构成的铁电电容器的顶部电极（图4d的308和310）和 铁电材料（图4d的306）位于顶部电极和底部电极之间，该方法包括以下步骤：在顶部电极上形成层（图4的408或312）; 在所述层中形成开口（图4d的414），以通过使用无氢蚀刻剂将所述开口蚀刻到所述层中来暴露所述顶部电极的一部分; 以及将导电材料（图4d的432）沉积在开口中以与顶部电极形成电连接。

    Damascene cap layer process for integrated circuit interconnects
    5.
    发明授权
    Damascene cap layer process for integrated circuit interconnects 有权
    用于集成电路互连的镶嵌帽层工艺

    公开(公告)号：US06410426B1

    公开(公告)日：2002-06-25

    申请号：US09901392

    申请日：2001-07-09

    申请人： Guoqiang Xing ,  Ping Jiang

    发明人： Guoqiang Xing ,  Ping Jiang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808 ,  H01L21/76802 ,  Y10S438/97

    摘要： The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k dielectric (4) which is filled with a conducting material (90) (95).

    摘要翻译： 本发明描述了一种用于形成集成电路互连的方法。 在低k电介质层（40）上形成覆盖层（50）。 蚀刻覆盖层（50）和低k电介质层（40）以在填充有导电材料（90）（95）的低k电介质（4）中形成通孔和/或沟槽。

    Hardmask designs for dry etching FeRAM capacitor stacks
    9.
    发明授权
    Hardmask designs for dry etching FeRAM capacitor stacks 有权
    硬掩模设计用于干蚀刻FeRAM电容器堆叠

    公开(公告)号：US06534809B2

    公开(公告)日：2003-03-18

    申请号：US09741479

    申请日：2000-12-19

    申请人： Theodore Moise ,  Stephen R. Gilbert ,  Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo

    发明人： Theodore Moise ,  Stephen R. Gilbert ,  Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo

    IPC分类号： H01L2994

    CPC分类号： H01L28/55 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139

    摘要： An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material (304 of FIG. 4a); a top electrode formed over the bottom electrode and comprised of a first electrode material (306and 308 of FIG. 4a); a ferroelectric material (306 of FIG. 4a) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer (402 of FIG. 4a) and a top hardmask layer (408 of FIG. 4a) formed on the bottom hardmask layer, the top hardmask layer able to with stand etchants used to etch the bottom electrode, the top electrode, and the ferroelectric material to leave the bottom hardmask layer substantially unremoved during the etch and the bottom hardmask layer being comprised of a conductive material which substantially acts as a hydrogen diffusion barrier.

    摘要翻译： 本发明的一个实施方案是形成在半导体衬底上的铁电电容器，所述铁电电容器包括：形成在所述半导体衬底上的底部电极，所述底部电极由底部电极材料（图4a的304）组成; 形成在底部电极上并由第一电极材料（图4a的306和308）组成的顶部电极; 位于顶部电极和底部电极之间的铁电材料（图4a的306） 以及形成在顶部电极上并包括底部硬掩模层（图4a的402）和形成在底部硬掩模层上的顶部硬掩模层（图4a的408）的硬掩模，所述顶部硬掩模层能够使用支架蚀刻剂 蚀刻底部电极，顶部电极和铁电材料以使蚀刻期间底部硬掩模层基本上不被去除，并且底部硬掩模层由基本上充当氢扩散阻挡层的导电材料构成。