公开(公告)号：US08299530B2

公开(公告)日：2012-10-30

申请号：US12717375

申请日：2010-03-04

申请人： Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

发明人： Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/12 ,  H01L21/8238

CPC分类号： H01L21/22 ,  H01L21/8238 ,  H01L27/092

摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.

摘要翻译： 提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为 适应平带，但不影响设备通道区域的功能。 该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。 所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。 沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。 该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。 通过离子注入或退火可形成局部功能调谐区域。

公开(公告)号：US20120184073A1

公开(公告)日：2012-07-19

申请号：US13433423

申请日：2012-03-29

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/792

摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.

摘要翻译： 提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。

公开(公告)号：US20120064694A1

公开(公告)日：2012-03-15

申请号：US12880419

申请日：2010-09-13

申请人： Roger A. BOOTH, JR. ,  Kangguo CHENG ,  Joseph ERVIN ,  Chengwen PEI ,  Ravi M. TODI ,  Geng WANG ,  Yanli ZHANG

发明人： Roger A. BOOTH, JR. ,  Kangguo CHENG ,  Joseph ERVIN ,  Chengwen PEI ,  Ravi M. TODI ,  Geng WANG ,  Yanli ZHANG

IPC分类号： H01L21/02

CPC分类号： H01L29/66181 ,  H01L27/1087

摘要： A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.

摘要翻译： 形成半导体器件的深沟槽结构的方法包括在半导体衬底上形成掩模层。 通过对掩模层进行构图来形成掩模层中的开口，并且使用掩模层中的图案化开口在半导体衬底中形成深沟槽。 牺牲填充材料形成在掩模层上并进入深沟槽中。 牺牲填充材料的第一部分从深沟槽凹陷，并且第一掺杂剂注入在半导体衬底中形成第一掺杂区域。 牺牲填充材料的第二部分从深沟槽凹陷，并且第二掺杂剂注入在半导体衬底中形成第二掺杂区，其中第二掺杂区形成在第一掺杂区的下方，使得第二掺杂区和第一掺杂区 掺杂区域彼此邻接。

公开(公告)号：US20110215321A1

公开(公告)日：2011-09-08

申请号：US12719289

申请日：2010-03-08

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Rainer Loesing ,  Chengwen Pei ,  Xiaojun Yu

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Rainer Loesing ,  Chengwen Pei ,  Xiaojun Yu

IPC分类号： H01L29/12 ,  H01L21/02 ,  H01L21/768 ,  H01L29/86 ,  H01L23/525

CPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/525 ,  H01L29/12 ,  H01L29/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.

摘要翻译： 提供了一种用于制造电阻性多晶半导体器件的方法，例如诸如半导体集成电路的微电子元件的多晶硅电阻器。 该方法可以包括：（a）形成层叠堆叠，其包括与衬底的单晶半导体区域的表面接触的电介质层，覆盖在电介质层上的金属栅极层，与金属栅极层相邻的第一多晶半导体区域， 掺杂剂类型的n或p，以及第二多晶半导体区域，其与所述第一多晶半导体区域与所述金属栅极层隔开并邻接所述第一多晶半导体区域; 和（b）形成与所述第二多晶半导体区域导电连通的第一和第二触点，所述第一和第二触点间隔开以达到期望的电阻。 在其变型中，形成电熔丝，其包括连续的硅化物区域，电流可以通过该硅化物区域通过以熔断熔丝。 在同一衬底上制造金属栅极场效应晶体管（FET）的同时可以同时采用制造多晶硅电阻器或电熔丝的步骤。

公开(公告)号：US07825479B2

公开(公告)日：2010-11-02

申请号：US12187003

申请日：2008-08-06

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei ,  Ravi M. Todi ,  Xiaojun Yu

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei ,  Ravi M. Todi ,  Xiaojun Yu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L23/5252 ,  H01L27/11206 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.

摘要翻译： 包括场效应晶体管的电反熔丝包括具有两个栅电介质部分的栅极电介质。 在栅极电介质上施加电场时，由于几何形状，在厚和薄栅介质部分之间的边界处，电场的幅度被局部增强，从而允许在两个电源电压之间的较低电源电压下对电反熔丝进行编程 电极，即晶体管的主体和栅电极，跨过栅极电介质。

公开(公告)号：US20090242953A1

公开(公告)日：2009-10-01

申请号：US12059174

申请日：2008-03-31

申请人： Roger A. Booth, JR. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

发明人： Roger A. Booth, JR. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

IPC分类号： H01L27/108 ,  H01L21/8242 ,  G06F17/50

CPC分类号： H01L27/0629

摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

摘要翻译： 通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。 第二极性可以与第一极性相反。 额外的植入物可以减少第二细胞中的ESR。

公开(公告)号：US07550773B2

公开(公告)日：2009-06-23

申请号：US11769032

申请日：2007-06-27

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman

IPC分类号： H01L29/04 ,  H01L31/036

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7855

摘要： FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconductor fin. The body or an extension of the body may be contacted above the channel or above one of the source and drain regions. Electrical shorts between the source and drain and the body contacts are avoided by the recessing of the source and drain regions from the top surface of the semiconductor fin.

摘要翻译： FinFET在半导体鳍片的顶表面上设有主体接触。 顶部本体接触可以相对于半导体鳍片和源极和漏极区域自对准。 或者，源极和漏极区域可以形成为从半导体鳍片的顶表面凹陷。 主体或身体的延伸部可以在通道上方或者源极和漏极区域之上接触。 通过源极和漏极区域从半导体鳍片的顶表面的凹陷来避免源极和漏极与主体接触之间的电短路。

公开(公告)号：US20090056998A1

公开(公告)日：2009-03-05

申请号：US11848330

申请日：2007-08-31

申请人： Roger A. Booth, Jr. ,  John R. Dangler ,  Matthew S. Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur K. Patel ,  Paul Rudrud

发明人： Roger A. Booth, Jr. ,  John R. Dangler ,  Matthew S. Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur K. Patel ,  Paul Rudrud

IPC分类号： H05K1/11 ,  H05K3/10

CPC分类号： H05K3/429 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09536 ,  H05K2201/09809 ,  H05K2203/061 ,  Y10T29/49165

摘要： Disclosed herein is a method comprising drilling a first hole in a multilayered device; the multilayered device comprising a fill layer disposed between and in intimate contact with two layers of a first electrically conducting material; the fill layer being electrically insulating; plating the first hole with a slurry; the slurry comprising a magnetic material, an electrically conducting material, or a combination comprising at least one of the foregoing materials; filling the first hole with a fill material; the fill material being electrically insulating; laminating a first layer and a second layer on opposing faces of the multilayered device to form a laminate; the opposing faces being the faces through which the first hole is drilled; the first layer and the second layer each comprising a second electrically conducting material; drilling a second hole through the laminate; the second hole having a circumference that is encompassed by a circumference of the first hole; and plating the surface of the second hole with a third electrically conducting material.

摘要翻译： 本文公开了一种方法，包括在多层装置中钻出第一孔; 所述多层器件包括设置在两层第一导电材料之间并与之紧密接触的填充层; 填充层电绝缘; 用浆料电镀第一个孔; 所述浆料包括磁性材料，导电材料或包含至少一种前述材料的组合; 用填充材料填充第一个孔; 填充材料电绝缘; 在所述多层器件的相对面上层叠第一层和第二层以形成层压体; 相对的面是钻出第一孔的面; 所述第一层和所述第二层各自包括第二导电材料; 穿过层压板钻出第二个孔; 所述第二孔具有由所述第一孔的圆周包围的圆周; 以及用第三导电材料电镀所述第二孔的表面。

公开(公告)号：US08916919B2

公开(公告)日：2014-12-23

申请号：US13167076

申请日：2011-06-23

申请人： Eric Thompson ,  Roger A. Booth, Jr. ,  Ning Lu ,  Christopher S. Putnam

发明人： Eric Thompson ,  Roger A. Booth, Jr. ,  Ning Lu ,  Christopher S. Putnam

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L23/522 ,  H01L27/02 ,  H01L49/02

CPC分类号： H01L23/5223 ,  H01L27/0207 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal capacitor structure includes a plurality of line level structures vertically interconnected with via level structures. Each first line level structure and each second line level structure includes a set of parallel metal lines that is physically joined at an end to a rectangular tab structure having a rectangular horizontal cross-sectional area. A first set of parallel metal lines within a first line level structure and a second set of parallel metal lines within a second line level structure are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure. Because the rectangular tab structures do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures, sub-resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure.

摘要翻译： 金属电容器结构包括与通孔层结构垂直相互连接的多个线路层结构。 每个第一行级别结构和每个第二行级结构包括一组平行金属线，其在端部物理连接到具有矩形水平横截面积的矩形突片结构。 第一线级结构内的第一组平行金属线和第二线级结构内的第二组平行金属线彼此交叉并且彼此平行，并且可以共同形成叉指的均匀间距结构。 由于矩形凸片结构在矩形凸片结构的两个相对的侧壁之间的区域内不会朝向彼此突出，所以可以采用副分辨率辅助特征（SRAF）来提供在整个交叉的整体上的均匀的宽度和均匀的间距 均匀节距结构。

公开(公告)号：US08809994B2

公开(公告)日：2014-08-19

申请号：US13316104

申请日：2011-12-09

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/70

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/945

摘要： Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

摘要翻译： 在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。 在沟槽中形成不透氧层和填充材料层。 从第一沟槽内去除填充材料层和不透氧层。 执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。 在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。 上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。