公开(公告)号：US07698482B2

公开(公告)日：2010-04-13

申请号：US11177007

申请日：2005-07-08

Applicant: Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

Inventor： Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

IPC: G06F3/00 ,  G06F5/00

CPC classification number: H03K19/17744

Abstract: A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.

Abstract translation: 用于可编程逻辑器件的串行接口通过提供支持第一范围的数据速率的第一数量的通道和支持第二数据速率范围的第二数量的通道来支持宽范围的数据速率。 数据速率的第一范围优选地低于数据速率的第二范围，并且优选地，第一数量的信道高于优选为1的信道的第二数量。为了与现有设备的向后兼容，每个信道中的第一数量的信道 界面最好是四。 每个通道优选地包括物理介质连接模块和物理编码子层模块。 第二数量的频道中的每一个较高频道优选地还包括时钟管理单元，而第一数量的频道中的较低速频道优选地共享一个或多个时钟管理单元。

公开(公告)号：US07577166B2

公开(公告)日：2009-08-18

申请号：US11189209

申请日：2005-07-26

Applicant: Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

Inventor： Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

IPC: H04J3/07

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H04J3/1617 ,  H04J2203/0082 ,  H04J2203/0094

Abstract: A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

Abstract translation: 可编程逻辑器件（“PLD”）包括通信接口电路，其可以支持任何广泛的通信协议，包括分组超声波（“POS-5”）和8位/ 10比特（“8B10B”）协议 。 接口电路包括至少部分硬连线以执行特定类型的功能的各种功能块，但是在至少许多情况下也可部分地可编程以允许基本功能适应各种协议。 对各种功能块之间，之间和/或周围的信号的路由也优选地至少可部分地可编程以便于以各种方式组合功能块来支持各种协议。

公开(公告)号：US07366267B1

公开(公告)日：2008-04-29

申请号：US10059014

申请日：2002-01-29

Applicant: Chong Lee ,  Ramanand Venkata

Inventor： Chong Lee ,  Ramanand Venkata

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  H03K5/135 ,  H03M9/00 ,  H04L7/0337

Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). THE CDR circuitry is provided with a programmable serializer and/or deserializer that can support higher data clock rates than the highest clock rate associated with the reference clock signal or clock signal from a phase locked loop circuit.

Abstract translation: 可编程逻辑器件（“PLD”）用可编程时钟数据恢复（“CDR”）电路进行增强，以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以与PLD集成，或者它可以全部或部分地在单独的集成电路上。 电路可能能够进行CDR输入，CDR输出或两者。 CDR能力可以与其他非CDR信令能力组合提供，例如非CDR低电压差分信号（“LVDS”）。 CDR电路配备有可编程串行器和/或解串器，其可以支持比与来自锁相环电路的参考时钟信号或时钟信号相关联的最高时钟速率更高的数据时钟速率。

公开(公告)号：US07305058B1

公开(公告)日：2007-12-04

申请号：US10317264

申请日：2002-12-10

Applicant: Ramanand Venkata ,  Chong H Lee

Inventor： Ramanand Venkata ,  Chong H Lee

IPC: H04L7/00

CPC classification number: H04L7/02 ,  H04J3/0632 ,  H04L7/005

Abstract: Clock rate matching circuitry is provided to buffer data between two clock domains that may have slightly different frequencies. To facilitate supporting a wide range of different communication protocols, the clock rate matching circuitry includes dedicated control circuitry and is also associated with other circuitry that is capable of acting as control circuitry that can be used as an alternative to at least part of the dedicated control circuitry. For example, the dedicated control circuitry may be set up to support one or several industry-standard protocols. The other circuitry (which may be, for example, programmable logic circuitry) is available to support any of a wide range of other protocols, whether industry-standard or custom.

Abstract translation: 提供时钟速率匹配电路以缓冲可能具有稍微不同频率的两个时钟域之间的数据。 为了便于支持各种不同的通信协议，时钟速率匹配电路包括专用控制电路，并且还与能够充当控制电路的其他电路相关联，该电路可用作至少部分专用控制的替代 电路。 例如，专用控制电路可以被设置为支持一个或多个行业标准协议。 其他电路（可能是例如可编程逻辑电路）可用于支持任何其他协议，无论是工业标准还是定制。

公开(公告)号：US20070139232A1

公开(公告)日：2007-06-21

申请号：US11655797

申请日：2007-01-18

Applicant: Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

Inventor： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

IPC: H03M7/00

CPC classification number: G06F13/385

Abstract: Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

公开(公告)号：US07183797B2

公开(公告)日：2007-02-27

申请号：US10977952

申请日：2004-10-29

Applicant: Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

Inventor： Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

IPC: H03K19/173

CPC classification number: G06F13/385

Abstract: Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

Abstract translation: 在具有支持更大范围的数据速率（例如，数据速率小于等于并且大于3.125Gbps）的能力的硬知识产权（IP）块中提供八位十位（8B10B）编码。 高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。 接收器和发射器电路可以配置为在三种工作模式之一下工作：级联模式，双通道模式和单通道模式。

公开(公告)号：US20070030184A1

公开(公告)日：2007-02-08

申请号：US11364589

申请日：2006-02-27

Applicant: Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

Inventor： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

IPC: H03M9/00

CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US07071726B1

公开(公告)日：2006-07-04

申请号：US11005390

申请日：2004-12-01

Applicant: Vinson Chan ,  Chong Lee ,  Rakesh Patel ,  Ramanand Venkata ,  Binh Ton

Inventor： Vinson Chan ,  Chong Lee ,  Rakesh Patel ,  Ramanand Venkata ,  Binh Ton

IPC: H03K19/00

CPC classification number: H03K19/17752 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17744

Abstract: Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.

Abstract translation: 提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。 根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。 这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。

公开(公告)号：US06970117B1

公开(公告)日：2005-11-29

申请号：US10789406

申请日：2004-02-26

Applicant: Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

Inventor： Henry Y. Lui ,  Chong H. Lee ,  Rakesh Patel ,  Ramanand Venkata ,  John Lam ,  Vinson Chan ,  Malik Kabani

IPC: H03M9/00 ,  H04L7/02

CPC classification number: H04L7/0054 ,  H03M9/00

Abstract: A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Abstract translation: 用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。 字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。 内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。 如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。 信号可以指示位滑动电路将边界调整校正对准所需的位数。 或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

公开(公告)号：US08571059B1

公开(公告)日：2013-10-29

申请号：US13194536

申请日：2011-07-29

Applicant: Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

Inventor： Arch Zaliznyak ,  Ramanand Venkata ,  Surinder Singh ,  Henry Y. Lui ,  Tim Tri Hoang ,  Sergey Shumarayev ,  Thungoc M. Tran

IPC: H04J3/00

CPC classification number: G06F13/385

Abstract: Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.

Abstract translation: 公开了用于提供具有共享数据路径的串行接口的装置和方法。 该装置和方法共享或重新使用来自多个低速数据路径的组件，以便有效地提供更高速度的数据通路。 在一个实施例中，低速数据路径的物理编码子层电路也被较高速数据路径使用。 在另一个实施例中，低速数据路径的物理介质访问电路也被高速数据路径使用。 还公开了其它实施例，方面和特征。