公开(公告)号：US07020012B2

公开(公告)日：2006-03-28

申请号：US11012059

申请日：2004-12-13

Applicant: Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier ,  Edmond R. Ward

Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier ,  Edmond R. Ward

IPC: G11C11/02

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/77

Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely defined. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage can be approximately equal to the average of the first select voltage and the second select voltage.

Abstract translation: 交叉点存储器阵列使用不同的电压。 本发明是一种交叉点存储器阵列，其在一个导电阵列线上施加第一选择电压，在第二导电阵列线上施加第二选择电压，两个导电阵列线是唯一限定的。 此外，未选择的电压被施加到未选择的导电阵列线。 可以在选择过程之前，之后或期间施加取消选择电压。 非选择电压可以近似等于第一选择电压和第二选择电压的平均值。

公开(公告)号：US07009235B2

公开(公告)日：2006-03-07

申请号：US10605963

申请日：2003-11-10

Applicant: Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier

Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier

IPC: H01L27/108

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.

Abstract translation: 提供导电存储器堆叠。 存储器堆叠包括底电极，顶电极和夹在电极之间的多电阻状态元件。 底电极可以被描述为具有第一表面区域的顶面，顶电极具有具有第二表面区域的底面，并且多电阻状态元件具有带有第三表面区域的底面和顶面 第四表面积。 多电阻状态元件的底面与底部电极的顶面接触，并且多电阻状态元件的顶面与顶部电极的底面接触。 此外，第四表面积不等于第二表面积。

公开(公告)号：US06834008B2

公开(公告)日：2004-12-21

申请号：US10330153

申请日：2002-12-26

Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

IPC: G11C1100

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  G11C2213/77

Abstract: Cross point memory array using multiple modes of operation. The invention is a cross point memory array that uses a read mode to determine the resistive state of a memory plug, a first write mode to cause the memory plug to change from a first resistive state to a second resistive state, and a second write mode to cause the memory plug to change from the second resistive state back to the first resistive state.

Abstract translation: 交叉点存储器阵列使用多种操作模式。 本发明是一种交叉点存储器阵列，其使用读取模式来确定存储器插头的电阻状态，使得存储器插头从第一电阻状态改变到第二电阻状态的第一写入模式和第二写入模式 以使存储器插头从第二电阻状态转变回第一电阻状态。

公开(公告)号：US06831854B2

公开(公告)日：2004-12-14

申请号：US10330964

申请日：2002-12-26

Applicant: Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

IPC: G11C1102

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/77

Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines uniquely defining a single memory plug. The magnitude of the select voltages depends upon whether a read operation or a write operation is occurring. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage is approximately equal to the average of the first select voltage and the second select voltage.

Abstract translation: 交叉点存储器阵列使用不同的电压。 本发明是一种交叉点存储器阵列，其在一个导电阵列线上施加第一选择电压，在第二导电阵列线上施加第二选择电压，所述两个导电阵列线唯一地限定单个存储器插头。 选择电压的大小取决于是否发生读取操作或写入操作。 此外，未选择的电压被施加到未选择的导电阵列线。 可以在选择过程之前，之后或期间施加取消选择电压。 取消选择电压近似等于第一选择电压和第二选择电压的平均值。

公开(公告)号：US06798685B2

公开(公告)日：2004-09-28

申请号：US10330150

申请日：2002-12-26

Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia

IPC: G11C1100

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

Abstract: Providing a multi-output multiplexor. The invention is multi-output multiplexor that, depending on the control signals, allows various modulating circuits to pass no voltage, pass some voltage or pass all the voltage on one of the multiplexor's ports. A modulating circuit can be fully turned on, partially turned on, or fully turned off. In a preferred embodiment, a gate circuit is in electrical contact with ground such that when the gate circuit is turned on and its associated modulating curcuit is not passing voltage, the multiplexor output associated with the modulating curcuit goes to ground.

Abstract translation: 提供多输出多路复用器。 本发明是多输出多路复用器，其根据控制信号允许各种调制电路不传递电压，传递一些电压或传递多路复用器端口之一上的所有电压。 调制电路可以完全打开，部分打开或完全关闭。 在优选实施例中，门电路与接地电接触，使得当门电路接通并且其相关联的调制电路不通过电压时，与调制电路相关联的多路复用器输出接地。

公开(公告)号：US07884349B2

公开(公告)日：2011-02-08

申请号：US12283339

申请日：2008-09-11

Applicant: Darrell Rinerson ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe J. Chevallier

Inventor： Darrell Rinerson ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe J. Chevallier

IPC: H01L29/06

CPC classification number: H01L27/101 ,  G11C11/00 ,  G11C11/56 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/00 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/147

Abstract: A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across the memory cell that are not read voltages operative read stored data from the memory element or write voltages operative to write data to the memory element. The selection device may comprise a pair of diodes that are electrically in series with each other and disposed in a back-to-back configuration. The memory cell may be fabricated over a substrate (e.g., a silicon wafer) that includes active circuitry. The selection device and the semiconductor materials (e.g., poly-silicon) that form the selection device are fabricated above the substrate and are integrated with other thin film layers of material that form the memory cell.

Abstract translation: 公开了一种包括彼此电串联的存储元件和非欧姆器件（NOD）的存储单元。 NOD包括基于半导体的选择装置，其操作以将存储器元件与施加在存储器单元上的电压范围电隔离，所述电压范围不是读取电压，从存储元件读取存储的数据，或者写入电压可操作以将数据写入存储器元件。 选择装置可以包括彼此电连接并以背对背配置设置的一对二极管。 可以在包括有源电路的衬底（例如，硅晶片）上制造存储器单元。 形成选择装置的选择装置和半导体材料（例如，多晶硅）制造在衬底之上，并与形成存储单元的材料的其它薄膜层集成。

公开(公告)号：US20100159641A1

公开(公告)日：2010-06-24

申请号：US12653851

申请日：2009-12-18

Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  David Hansen ,  Robin Cheung ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  David Hansen ,  Robin Cheung ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

IPC: H01L21/34

CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

公开(公告)号：US07439082B2

公开(公告)日：2008-10-21

申请号：US11369663

申请日：2006-03-06

Applicant: Darrell Rinerson ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia

Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia

IPC: H01L21/8242

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.

Abstract translation: 提供导电存储器堆叠。 存储器堆叠包括底电极，顶电极和夹在电极之间的多电阻状态元件。 底电极可以被描述为具有第一表面区域的顶面，顶电极具有具有第二表面区域的底面，并且多电阻状态元件具有带有第三表面区域的底面和顶面 第四表面积。 多电阻状态元件的底面与底部电极的顶面接触，并且多电阻状态元件的顶面与顶部电极的底面接触。 此外，第四表面积不等于第二表面积。

公开(公告)号：US07382644B2

公开(公告)日：2008-06-03

申请号：US11725045

申请日：2007-03-16

Applicant: Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77

Abstract: A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.

公开(公告)号：US07095643B2

公开(公告)日：2006-08-22

申请号：US11151880

申请日：2005-06-13

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward

IPC: G11C5/06

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31

Abstract: A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

Abstract translation: 具有多个内存层的可重写内存。 只要存在只有一个选择了两个端子的存储单元，就可以选择使用层叠交叉点结构中的存储单元的两个端子进行选择，以便选择多层导电线。 通过多层共享逻辑可以重新使用驱动程序集。