公开(公告)号：US20030154043A1

公开(公告)日：2003-08-14

申请号：US10327705

申请日：2002-12-20

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Balwant Singh

IPC: G06F019/00 ,  G01R025/00 ,  G01R029/02

CPC classification number: G01R31/2882 ,  G01R29/02 ,  G01R31/3016 ,  G01R31/31937

Abstract: A system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge of said measuring clock pulses. Further, the invention measures the delay count obtained from said chain of cascaded delay elements from the trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adds said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.

公开(公告)号：US20030063026A1

公开(公告)日：2003-04-03

申请号：US10255153

申请日：2002-09-25

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Tapas Nandy

IPC: H03M001/12

CPC classification number: H03M1/0854 ,  H03M1/468 ,  H03M1/804

Abstract: An improved binary-weighted, switched-capacitor, charge-redistribution successive approximation analog-to-digital converter (ADC) may include an adjusting mechanism for adding a charge corresponding to one-half of the least significant bit (LSB) of the ADC to the charge stored in a switched capacitor array thereof after the sampling phase of the ADC. This is done to provide a quantization error that is evenly distributed between null0.5 times the LSB, without the need for any additional processing clock cycles.

Abstract translation: 改进的二进制加权，开关电容器，电荷再分配逐次逼近模数转换器（ADC）可以包括调整机制，用于将对应于ADC的最低有效位（LSB）的一半的电荷加到 在ADC的采样相位之后存储在其开关电容器阵列中的电荷。 这是为了提供均匀分布在LSB的±0.5倍之间的量化误差，而不需要任何额外的处理时钟周期。

公开(公告)号：US20140013177A1

公开(公告)日：2014-01-09

申请号：US14019329

申请日：2013-09-05

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Parul Bansal

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G06F11/3656

Abstract: An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.

Abstract translation: 片上功能调试器包括一个或多个功能块，每个功能块提供一个或多个功能输出。 分层选择树由具有选择器之一的输出的一个或多个选择器形成为最终输出，以及耦合到功能块的功能输出或另一个选择器的输出的单独选择器输入。 选择信号，其耦合到每个选择器的选择输入以使得其输出中的所选择的一个。 耦合到最终输出的输出节点。 还提供了一种提供片上功能调试的方法。 选择来自一个或多个可用功能输出的期望的功能输出，然后所选择的功能输出耦合到输出节点。

公开(公告)号：US20040178821A1

公开(公告)日：2004-09-16

申请号：US10739395

申请日：2003-12-18

Applicant: STMICROELECTRONICS PVT. LTD.

Inventor： Ankur Bal ,  Namerita Khanna

IPC: H03K019/177

CPC classification number: H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

Abstract translation: 本发明涉及一种高性能互连架构，其提供减少的延迟最小化的电迁移和FPGA中的减少的区域，包括由互连的逻辑块组成的多个瓦片，其由中间的逻辑块分隔。 每组相互连接的逻辑块由互连段链接，该互连段通过互连层在中间逻辑块上以直线路由，并且通过连接段选择性地连接到每端的逻辑块。

公开(公告)号：US20040070422A1

公开(公告)日：2004-04-15

申请号：US10608854

申请日：2003-06-27

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Sushma Mohan ,  Parvesh Swami

IPC: H03K019/177

CPC classification number: H03K19/17728 ,  H03K19/1737

Abstract: A Programmable Logic Device (PLD) incorporating a plurality of Programmable Logic Blocks (PLBS) providing enhanced flexibility for Cascade logic functions, each comprising a multi-input Look Up Table (LUT) providing one input to a Cascade Logic block for implementing desired Cascade Logic functions. The other input of the Cascade Logic block is a Cascade-In signal. A 2-input selection multiplexer receives one input from the output of the Cascade Logic block and the other from the output of the LUT for selecting either the Cascade Logic output or the LUT output as the unregistered output. The arrangement is such that the Cascade output and the multiplexer output are simultaneously available from the PLB.

Abstract translation: 一种包含多个可编程逻辑块（PLBS）的可编程逻辑器件（PLD），其为级联逻辑功能提供增强的灵活性，每个逻辑器件包括多输入查找表（LUT），其为级联逻辑块提供一个输入，以实现所需的级联逻辑 功能。 级联逻辑块的另一个输入是级联输入信号。 2输入选择多路复用器从串级逻辑块的输出接收一个输入，而从LUT的输出接收另一个输入，用于选择级联逻辑输出或LUT输出作为未注册输出。 这种布置使得级联输出和多路复用器输出可以从PLB同时获得。

公开(公告)号：US20040036499A1

公开(公告)日：2004-02-26

申请号：US10464420

申请日：2003-06-17

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Ankur Bal

IPC: H03K019/173

CPC classification number: H03K19/17736 ,  H03K19/17796

Abstract: An FPCA includes a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxes at the periphery for maintaining constant routing channel width.

Abstract translation: FPCA包括用于外围路由的方​​案，其通过并入正交对称偏转的相等长度的外围路由线来提供包括外围在内的整个区域的对称路由。 对称的外围路由线路连接到外围的交换机和连接盒，以保持不断的路由信道宽度。

公开(公告)号：US20040015758A1

公开(公告)日：2004-01-22

申请号：US10436895

申请日：2003-05-13

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Shalini Pathak ,  Parvesh Swami

IPC: G01R031/28

CPC classification number: G11C29/025 ,  G01R31/318516 ,  G11C29/02 ,  G11C29/12

Abstract: A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.

Abstract translation: 可编程逻辑器件（PLD）能够独立地或在配置期间测试配置存储器。 PLD可以包括用于选择配置存储器阵列的特定列或行的选择器，以及用于存储需要存储在所选列或行中的配置数据的输入数据存储装置，或用于测试所选列或行的测试数据 。 PLD还可以包括用于存储来自所选择的列或行的输出的输出数据存储装置以及提供用于验证配置存储器阵列的数据线的正确操作的控制信号而不干扰存储在存储器中的数据的测试逻辑 数组。

公开(公告)号：US20040008055A1

公开(公告)日：2004-01-15

申请号：US10449750

申请日：2003-05-29

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Namerita Khanna ,  Parvesh Swami ,  Deepak Agarwal

IPC: H03K019/177

CPC classification number: H03K19/1776 ,  H03K3/012 ,  H03K3/037 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17784

Abstract: A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Abstract translation: 一种可编程逻辑器件，用于为顺序逻辑和数据存储功能提供功率消耗降低，包括至少一个电路装置，其可配置为在电路时钟选定的一个或两个边缘上工作的双边沿触发触发器。

公开(公告)号：US20030214321A1

公开(公告)日：2003-11-20

申请号：US10407802

申请日：2003-04-04

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

IPC: H03K019/173

CPC classification number: H03K19/17736

Abstract: An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

Abstract translation: 一种改进的可编程逻辑设备架构，其通过在设备中的任何其他PLB上访问任何可编程逻辑块（PLB）的域中的定义的电路元件来提供资源的更有效的利用，通过在路由结构中并入选择性地连接 将PLB域中的电路元件的输入或输出连接到将所有PLB连接在一起的公共互连矩阵。

公开(公告)号：US20030117868A1

公开(公告)日：2003-06-26

申请号：US10321297

申请日：2002-12-17

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Balwant Singh

IPC: G11C007/00

CPC classification number: G11C29/50012 ,  G11C29/50

Abstract: A system for measuring a timing skew between two digital signals may include a clock generator for generating a time measurement clock, and a pulse-to-digital converter for converting the timing skew into an equivalent digital coded value after correcting for internal logic delays. The system may further include a register bank for storing the digital coded values, and a controller for generating control signals and sequences for controlling the operation of the pulse-to-digital converter and the register bank.

Abstract translation: 用于测量两个数字信号之间的定时偏差的系统可以包括用于产生时间测量时钟的时钟发生器和用于在校正内部逻辑延迟之后将定时偏差转换为等效数字编码值的脉冲 - 数字转换器。 该系统还可以包括用于存储数字编码值的寄存器组，以及用于产生用于控制脉冲数字转换器和寄存器组的操作的控制信号和序列的控制器。