中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.014 seconds)

    Shape memory device
    31.
    发明授权
    Shape memory device 有权
    形状记忆装置

    公开(公告)号：US08553455B2

    公开(公告)日：2013-10-08

    申请号：US11528712

    申请日：2006-09-27

    Applicant: Sandip Tiwari ,  Chung Woo Kim

    Inventor： Sandip Tiwari ,  Chung Woo Kim

    IPC: G11C11/34

    CPC classification number: H01L27/115 ,  B81B3/0072 ,  B81B2201/016 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/14 ,  G11C2213/17 ,  G11C2213/77 ,  H01H9/547 ,  H01H59/0009 ,  H01H61/0107 ,  H01L21/28273 ,  H01L27/112 ,  H01L29/66825 ,  H01L29/785

    Abstract: Mechanical devices having bistable positions are utilized to form switches and memory devices. The devices are actuatable to different positions and may be coupled to a transistor device in various configurations to provide memory devices. Actuation mechanisms include electrostatic methods and heat. In one form, the mechanical device forms a gate for a field effect transistor. In a further form, the device may be a switch that may be coupled to the transistor in various manners to affect its electrical characteristics when on and off. The memory switch in one embodiment comprises side walls formed with tensile or compressive films. A cross point switch is formed from a plurality of intersecting conductive rows and columns of conductors. Actuatable switches are positioned between each intersection of the rows and columns such that each intersection is independently addressable.

    Abstract translation: 利用具有双稳态位置的机械装置来形成开关和存储装置。 这些器件可被驱动到不同的位置，并且可以以各种配置耦合到晶体管器件以提供存储器件。 致动机制包括静电法和热量。 在一种形式中，机械装置形成用于场效应晶体管的栅极。 在另一种形式中，器件可以是开关，其可以以各种方式耦合到晶体管，以便在接通和断开时影响其电特性。 在一个实施例中的存储器开关包括由拉伸或压缩膜形成的侧壁。 交叉点开关由多个交叉的导电行和导体列形成。 可执行开关位于行和列的每个交叉点之间，使得每个交叉点可独立寻址。

    Electronic gain cell based charge sensor
    32.
    发明授权
    Electronic gain cell based charge sensor 有权
    基于电子增益单元的电荷传感器

    公开(公告)号：US06953958B2

    公开(公告)日：2005-10-11

    申请号：US10393515

    申请日：2003-03-19

    Applicant: Gregory T. Baxter ,  Sandip Tiwari

    Inventor： Gregory T. Baxter ,  Sandip Tiwari

    IPC: G11C11/54 ,  G11C13/02 ,  H01L23/58

    CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C11/54 ,  G11C13/02 ,  G11C2216/08 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A gated metal oxide semiconductor field effect transistor (MOSFET) gain cell is formed with a flow channel for molecule flow. The flow channel is formed under the gate, and between a source and drain of the transistor. The molecule flow modulates a gain of the transistor. Current flowing between the source and drain is representative of charges on the molecules flowing through the flow channel. A plurality of individually addressable gain cells are coupled between chambers containing samples to measure charges on molecules in the samples passing through the gain cells.

    Abstract translation: 栅极金属氧化物半导体场效应晶体管（MOSFET）增益单元形成有用于分子流的流动通道。 流通道形成在栅极下方，并在晶体管的源极和漏极之间。 分子流调制晶体管的增益。 在源极和漏极之间流动的电流代表流过流动通道的分子上的电荷。 多个可单独寻址的增益单元耦合在包含样本的室之间以测量通过增益单元的样品中的分子上的电荷。

    Method of forming self-isolated and self-aligned 4F-square vertical FET-trench DRAM cells
    33.
    发明授权
    Method of forming self-isolated and self-aligned 4F-square vertical FET-trench DRAM cells 失效
    形成自隔离和自对准4F方形垂直FET沟槽DRAM单元的方法

    公开(公告)号：US06316309B1

    公开(公告)日：2001-11-13

    申请号：US09626332

    申请日：2000-07-26

    Applicant: Steven John Holmes ,  Howard Leo Kalter ,  Sandip Tiwari ,  Jeffrey John Welser

    Inventor： Steven John Holmes ,  Howard Leo Kalter ,  Sandip Tiwari ,  Jeffrey John Welser

    IPC: H01L218242

    CPC classification number: H01L27/10864 ,  H01L27/10823 ,  H01L27/1087 ,  H01L29/945

    Abstract: A densely packed array of vertical semiconductor devices, having pillars, deep trench capacitors, vertical transistors, and methods of making thereof are disclosed. The pillars act as transistor channels, and may be formed utilizing the application of hybrid resist over a block of semiconductor material. Drain doped regions are formed on the top of each pillar. The source doped regions and the plate doped regions are self-aligned and are created by diffusion in the trenches surrounding the pillars. The array has columns of bitlines and rows of wordlines. The capacitors are formed by isolating n+ polysilicon in trenches separating said pillars. The array is suitable for GBit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline architecture, where the plate region is common to all the storage nodes or a folded architecture with two wordlines that pass through each cell having stacked transistors, where one wordline is active and the other is passing for each cell.

    Abstract translation: 公开了一种密集堆叠的垂直半导体器件阵列，具有支柱，深沟槽电容器，垂直晶体管及其制造方法。 支柱用作晶体管通道，并且可以利用在半导体材料块上施加混合抗蚀剂来形成。 在每个支柱的顶部形成漏极掺杂区域。 源掺杂区域和板掺杂区域是自对准的，并且通过在柱子周围的沟槽中的扩散而产生。 该阵列具有位线和字线行。 通过在分离所述柱的沟槽中隔离n +多晶硅来形成电容器。 该阵列适用于GBit DRAM应用，因为深沟槽电容器不增加阵列面积。 阵列可以具有开放的位线架构，其中板区域对于所有存储节点是公共的，或者具有两个字线的折叠结构，其中两个字线通过具有堆叠晶体管的每个单元，其中一个字线是活动的，而另一个字线通过每个单元。

    Light emitting structures in back-end of line silicon technology
    35.
    发明授权
    Light emitting structures in back-end of line silicon technology 失效
    线硅技术后端发光结构

    公开(公告)号：US06236060B1

    公开(公告)日：2001-05-22

    申请号：US08974215

    申请日：1997-11-19

    Applicant: Kevin Kok Chan ,  Sandip Tiwari

    Inventor： Kevin Kok Chan ,  Sandip Tiwari

    IPC: H01L2906

    CPC classification number: H01L33/08

    Abstract: A light emitting device is disclosed comprising a bottom layer of electrically conductive material. A block of electrically insulating material is disposed on the bottom layer. At least a portion of the block is optically transparent. A top layer of electrically conductive material is disposed on the block. A plurality of discrete nano-crystals of a material selected from the group consisting of Group IV, Group III-V, and Group II-VI is disposed within the block, and are thereby electrically insulated from the top and bottom layers. Also provided are bottom and top electrodes connected to the bottom and top layers, respectively, for applying a voltage therebetween.

    Abstract translation: 公开了一种发光器件，其包括导电材料的底层。 一层电绝缘材料设置在底层上。 块的至少一部分是光学透明的。 导电材料的顶层设置在块上。 选自由组IV，组III-V和组II-VI组成的组的材料的多个离散纳米晶体设置在所述块内，并且由此与顶层和底层电绝缘。 还提供了分别连接到底层和顶层的底部和顶部电极，用于在它们之间施加电压。

    Two transistor single capacitor ferroelectric memory
    36.
    发明授权
    Two transistor single capacitor ferroelectric memory 失效
    双晶体管单电容器铁电存储器

    公开(公告)号：US6101117A

    公开(公告)日：2000-08-08

    申请号：US273795

    申请日：1999-03-22

    Applicant: Sandip Tiwari

    Inventor： Sandip Tiwari

    IPC: H01L21/8247 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

    CPC classification number: G11C11/22

    Abstract: A back-plane ferroelectric memory apparatus employing a read transistor, a write transistor and a ferroelectric capacitor storage means. A back plane forms a gate region underneath the read transistor with the potential of the back plane affected by polarization of the ferroelectric capacitor. The write and read transistors are different, the write transistor may be a vertical structure and the read transistor may be a write transistor and the write transistor's drain is connected to the back plane of read transistor and a plate of the ferroelectric capacitor.

    Abstract translation: 采用读取晶体管，写入晶体管和铁电电容器存储装置的背面铁电存储装置。 背面在读取晶体管的下面形成栅极区域，其背面的电位受到铁电电容器极化的影响。 写入和读取晶体管是不同的，写入晶体管可以是垂直结构，并且读取晶体管可以是写入晶体管，并且写入晶体管的漏极连接到读取晶体管的背板和铁电电容器的板。

    Unpinned oxide-compound semiconductor structures and method of forming same
    39.
    发明授权
    Unpinned oxide-compound semiconductor structures and method of forming same 失效
    未固定的氧化物 - 半导体结构及其形成方法

    公开(公告)号：US5086321A

    公开(公告)日：1992-02-04

    申请号：US592611

    申请日：1990-10-04

    Applicant: John Batey ,  Sandip Tiwari ,  Steven L. Wright

    Inventor： John Batey ,  Sandip Tiwari ,  Steven L. Wright

    IPC: H01L21/28 ,  H01L21/314 ,  H01L21/336 ,  H01L29/267 ,  H01L29/43

    CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L21/314 ,  H01L29/267 ,  H01L29/432

    Abstract: Unpinned epitaxial metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor are grown by MBE which result in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer is deposited epitaxially in situ with the compound semiconductor layer which unpins the surface Fermi level. A layer of insulator material is then deposited on the elemental semiconductor layer by PECVD. In one embodiment, the compound semiconductor is GaAs and the elemental semiconductor is Si. The insulator material is a layer of high quality SiO.sub.2. A metal gate is deposited on the SiO.sub.2 layer to form an MOS device. The epitaxial GaAs layer has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO.sub.2 deposition completely consumes the interface Si layer so that the resulting MOS device comprises SiO.sub.2 directly overlying the GaAs layer.

    Abstract translation: 公开了未连接的外延金属氧化物半导体结构，并描述了制造这种结构的方法。 通过MBE生长化合物半导体的外延层，这导致形成具有稳定重建的光滑表面。 原位沉积元素半导体层，其中化合物半导体层取代了表面费米能级。 然后通过PECVD将绝缘体材料层沉积在元素半导体层上。 在一个实施例中，化合物半导体是GaAs，元素半导体是Si。 绝缘材料是一层高质量的SiO2。 金属栅极沉积在SiO 2层上以形成MOS器件。 外延GaAs层具有允许接口费米能级移动通过整个禁止能隙的状态密度。 在另一个实施例中，SiO 2沉积完全消耗界面Si层，使得所得的MOS器件包括直接覆盖GaAs层的SiO 2。

    Heterostructure bipolar transistor
    40.
    发明授权
    Heterostructure bipolar transistor 失效
    异质结双极晶体管

    公开(公告)号：US4586071A

    公开(公告)日：1986-04-29

    申请号：US609406

    申请日：1984-05-11

    Applicant: Sandip Tiwari

    Inventor： Sandip Tiwari

    IPC: H01L29/205 ,  H01L21/331 ,  H01L29/20 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L29/72

    CPC classification number: H01L29/475 ,  H01L29/42304 ,  H01L29/452 ,  H01L29/7327 ,  H01L29/7371 ,  Y10S148/01 ,  Y10S148/084 ,  Y10S148/14

    Abstract: A heterojunction bipolar transistor having an ohmic contact at the intersection of the base and an adjacent region serving as emitter or collector that forms an ohmic contact to the base and a Schottky barrier to the adjacent emitter or collector. A GaAs-GaAlAs device with a platinum or palladium electrode over the intersection between collector and base and forming an ohmic contact to a p-base region and a Schottky barrier with an n-collector region thereof.

    Abstract translation: 一种异质结双极晶体管，在基极和用作发射极或集电极的相邻区域的交点处具有欧姆接触，与基极形成欧姆接触，对相邻的发射极或集电极形成肖特基势垒。 一种GaAs-GaAlAs器件，其在集电极和基极之间的交叉点上具有铂或钯电极，并形成与p基极区域的欧姆接触和具有n极集电极区域的肖特基势垒。

Patent Agency Ranking