公开(公告)号：US20050082601A1

公开(公告)日：2005-04-21

申请号：US10689462

申请日：2003-10-20

申请人： Wen-Ting Chu ,  Shih-Chang Liu

发明人： Wen-Ting Chu ,  Shih-Chang Liu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A method of forming a split gate field effect transistor and a structure of the split gate field effect transistor are provided. The method of forming the split gate effect transistor firstly provides a substrate having a pair of floating gates, a first conductive material layer between the pair of floating gates, and a first dielectric layer above the first conductive material layer. Then a control gate is formed. The control gate has a second dielectric layer above the control gate, wherein the control gate is self-aligned to the pair of floating gates by using the first and second dielectric layers as an etching hard mask. Finally, a pair of source/drain regions are formed into said substrate and beside said pair of floating gates and said control gate.

摘要翻译： 提供了形成分裂栅极场效应晶体管的方法和分离栅极场效应晶体管的结构。 形成分裂栅效应晶体管的方法首先提供了具有一对浮置栅极的衬底，在一对浮置栅极之间的第一导电材料层和位于第一导电材料层上方的第一电介质层。 然后形成控制门。 控制栅极具有在控制栅极上方的第二介电层，其中通过使用第一和第二介电层作为蚀刻硬掩模，控制栅极与一对浮置栅极自对准。 最后，一对源极/漏极区域形成在所述衬底中以及所述一对浮置栅极和所述控制栅极旁边。

公开(公告)号：US10553785B2

公开(公告)日：2020-02-04

申请号：US13452230

申请日：2012-04-20

申请人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

摘要： This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit.

公开(公告)号：US08629531B2

公开(公告)日：2014-01-14

申请号：US13030645

申请日：2011-02-18

申请人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L21/20 ,  H01L21/18

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/107 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/007 ,  H01L33/12

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.

摘要翻译： 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。

公开(公告)号：US08569849B2

公开(公告)日：2013-10-29

申请号：US13618908

申请日：2012-09-14

申请人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

发明人： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  G11C11/16

摘要： A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

摘要翻译： 提供半导体器件和制造方法，例如MTJ器件和制造MTJ器件的方法。 MTJ装置可以包括底部电极，MTJ堆叠和顶部电极，其中顶部电极使用填充孔技术形成。 顶部电极可以具有倾斜的侧壁。 可以通过沉积相应的MTJ层来形成MTJ堆叠。 可以在MTJ层上形成并图案化图案化掩模以形成限定顶部电极的开口。 开口填充有导电材料以形成顶部电极。 然后将顶部电极用作掩模以对MTJ层进行图案化，从而形成MTJ堆叠。

公开(公告)号：US20130026585A1

公开(公告)日：2013-01-31

申请号：US13190966

申请日：2011-07-26

申请人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L43/12 ,  H01L43/08

摘要： According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

公开(公告)号：US20120261781A1

公开(公告)日：2012-10-18

申请号：US13087192

申请日：2011-04-14

申请人： Hung-Wen Hsu ,  Shih-Chang Liu ,  Yeur-Luen Tu

发明人： Hung-Wen Hsu ,  Shih-Chang Liu ,  Yeur-Luen Tu

IPC分类号： H01L27/146 ,  H01L31/18

CPC分类号： H01L27/14685 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1464

摘要： The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature.

摘要翻译： 本公开提供了一种图像传感器装置和用于制造图像传感器装置的方法。 示例性的图像传感器装置包括具有前表面和后表面的基板; 设置在所述基板的前表面处的多个传感器元件，所述多个传感器元件中的每一个可操作以感测朝向所述基板的后表面投射的辐射; 辐射屏蔽特征设置在所述基板的所述背表面上并且水平地设置在所述多个传感器元件中的每一个之间; 设置在基板的背面和辐射屏蔽特征之间的电介质特征; 以及沿着电介质特征的侧壁设置的金属层。

公开(公告)号：US20120211759A1

公开(公告)日：2012-08-23

申请号：US13030645

申请日：2011-02-18

申请人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L29/20 ,  H01L21/20

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/107 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/007 ,  H01L33/12

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.

摘要翻译： 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。

公开(公告)号：US08227850B2

公开(公告)日：2012-07-24

申请号：US12723381

申请日：2010-03-12

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L29/76

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

公开(公告)号：US08114740B2

公开(公告)日：2012-02-14

申请号：US13045955

申请日：2011-03-11

申请人： Shih-Chang Liu ,  Chu-Wei Chang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chu-Wei Chang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

摘要： A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的隧道层; 邻近隧道层的源区; 和隧道层上的浮动栅极。 浮动门包括具有上部和下部的第一边缘，其中下部从上部凹进。 半导体结构还包括在浮置栅极上的阻挡层，其中阻挡层具有面向与浮动栅极的第一边缘相同方向的第一边缘。

公开(公告)号：US20110189796A1

公开(公告)日：2011-08-04

申请号：US12696771

申请日：2010-01-29

申请人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  H01L27/222

摘要： A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

摘要翻译： 形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。 在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带 电介质层并连接到顶部电极。