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    Semiconductor memory having burst transfer function and internal refresh function
    32.
    发明授权
    Semiconductor memory having burst transfer function and internal refresh function 有权
    具有突发传输功能和内部刷新功能的半导体存储器

    公开(公告)号：US06847570B2

    公开(公告)日：2005-01-25

    申请号：US10300800

    申请日：2002-11-21

    申请人： Shinya Fujioka ,  Yoshiaki Okuyama

    发明人： Shinya Fujioka ,  Yoshiaki Okuyama

    IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076

    摘要： A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.

    摘要翻译： 刷新控制电路以预定的周期生成刷新请求。 第一突发控制电路根据访问命令输出预定数量的选通信号。 通过访问命令执行突发存取操作。 数据输入/输出电路连续输入要传送到存储单元阵列的数据，或者与选通信号同步地连续输出从存储单元阵列提供的数据。 当刷新请求和访问命令彼此冲突时，仲裁器确定首先执行刷新操作或突发存取操作中的哪一个。 因此，可以顺序地执行刷新操作和突发存取操作而不重叠。 结果，可以高速地输出读取数据，并且可以高速地输入写入数据。 也就是说，可以提高数据传输速率。

    Semiconductor memory device having an SRAM and a DRAM on a single chip
    33.
    发明授权
    Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
    在单个芯片上具有SRAM和DRAM的半导体存储器件

    公开(公告)号：US06735141B2

    公开(公告)日：2004-05-11

    申请号：US09917913

    申请日：2001-07-31

    申请人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    发明人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    IPC分类号： G11C700

    CPC分类号： G11C11/005

    摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

    摘要翻译： 半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。 在芯片上提供DRAM，DRAM包括DRAM单元阵列。 地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值 ，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

    Semiconductor memory
    34.
    发明授权
    Semiconductor memory 有权

    公开(公告)号：US06621750B2

    公开(公告)日：2003-09-16

    申请号：US10155029

    申请日：2002-05-28

    申请人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

    发明人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

    IPC分类号： G11C700

    CPC分类号： G11C29/808 ,  G11C29/812 ,  G11C29/848

    摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

    Dynamic random access memory having a low power consumption mode, and method of operating the same
    35.
    发明授权
    Dynamic random access memory having a low power consumption mode, and method of operating the same 有权
    具有低功耗模式的动态随机存取存储器及其操作方法

    公开(公告)号：US06584032B2

    公开(公告)日：2003-06-24

    申请号：US09949847

    申请日：2001-09-12

    申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

    发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

    IPC分类号： G11C700

    CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

    摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。

    Fuse circuit
    36.
    发明授权
    Fuse circuit 有权
    保险丝电路

    公开(公告)号：US06566937B1

    公开(公告)日：2003-05-20

    申请号：US10152579

    申请日：2002-05-23

    申请人： Katsuhiro Mori ,  Shinya Fujioka ,  Masahiro Niimi

    发明人： Katsuhiro Mori ,  Shinya Fujioka ,  Masahiro Niimi

    IPC分类号： H01H3776

    CPC分类号： G11C17/16

    摘要： Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

    摘要翻译： 在第一周期的前半段通过第三开关接收到第二节点的电平时，保持电路将其作为指示保险丝的熔断状态的熔丝信号输出。 由于在第一周期的后半部分中第三开关断开，所以其后发生的第二节点的电平变化不会影响保持电路中的数据，从而防止熔丝电路的故障。 在保险丝熔断时，在第一周期之后，第一节点的电平固定在第二电源线的电平上。 这消除了保险丝两端之间的电压差，从而防止了长时间的恢复。 即使没有完全切断保险丝，也不会发生长时间退回，只有一个保险丝对保险丝电路充足。 从而缩短了在测试过程中熔断熔断器的时间。

    Semiconductor device
    39.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06498522B2

    公开(公告)日：2002-12-24

    申请号：US09833045

    申请日：2001-04-12

    申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Yasuharu Sato ,  Yasurou Matsuzaki

    发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Yasuharu Sato ,  Yasurou Matsuzaki

    IPC分类号： H03L700

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222

    摘要： The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.

    摘要翻译： 本发明涉及一种时钟同步型半导体器件，其与时钟信号同步地接收从外部输入的输入信号。 根据本发明的半导体器件包括输入信号接收单元，其接收从外部输入的输入信号，其中接收与时钟信号同步完成; 时钟定时选择单元，用于输出时钟选择信号; 以及时钟发生单元，响应于接收到时钟选择信号和外部时钟信号，在与时钟选择信号的信号电平相对应的预定定时产生时钟信号，并将时钟信号输出到输入信号 接收单元，其中无论外部时钟信号的频率如何，都可以安全地接受输入信号。

    Constant-current generator, differential amplifier, and semiconductor integrated circuit
    40.
    发明授权
    Constant-current generator, differential amplifier, and semiconductor integrated circuit 有权
    恒流发电机，差分放大器和半导体集成电路

    公开(公告)号：US06452453B1

    公开(公告)日：2002-09-17

    申请号：US09562289

    申请日：2000-05-01

    申请人： Shinya Fujioka ,  Akihiro Funyu

    发明人： Shinya Fujioka ,  Akihiro Funyu

    IPC分类号： H03F304

    CPC分类号： H03F1/301 ,  H03F2203/45456 ,  H03F2203/45508

    摘要： The constant-current generator comprises a bias transistor whose drain and gate are connected to each other, and an outputting transistor. The threshold voltage of the outputting transistor is smaller than that of the bias transistor. The outputting transistor has the same source voltage and the same gate voltage as those of the bias transistor. Therefore, the gate-to-source voltages of the outputting transistor and the bias transistor are always kept equal. On the other hand, the drain-to-source current of the outputting transistor becomes larger than that of the bias transistor in accordance with the difference between the threshold voltages of the outputting transistor and the bias transistor. Accordingly, the outputting transistor can output a stable drain-to-source current even when the drain voltage of the bias transistor has shifted to lower the gate-to-source voltage thereof.

    摘要翻译： 恒流发生器包括漏极和栅极彼此连接的偏置晶体管和输出晶体管。 输出晶体管的阈值电压小于偏置晶体管的阈值电压。 输出晶体管具有与偏置晶体管相同的源极电压和相同的栅极电压。 因此，输出晶体管和偏置晶体管的栅极 - 源极电压总是保持相等。 另一方面，根据输出晶体管和偏置晶体管的阈值电压之差，输出晶体管的漏极 - 源极电流变得大于偏置晶体管的漏极 - 源极电流。 因此，即使当偏置晶体管的漏极电压已经偏移以降低其栅极至源极电压时，输出晶体管也可以输出稳定的漏极 - 源极电流。