公开(公告)号：US08373238B2

公开(公告)日：2013-02-12

申请号：US12843595

申请日：2010-07-26

Applicant: Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

Inventor： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC: H01L27/088

CPC classification number: H01L29/66666 ,  H01L21/76 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.

Abstract translation: 集成电路结构包括半导体衬底和半导体衬底上的FinFET。 FinFET包括半导体鳍片; 顶表面上的栅极电介质和半导体鳍片的侧壁; 栅电极上的栅电极; 以及在半导体鳍片的端部处的源极/漏极区域。 第一对浅沟槽隔离（STI）区域包括直接在源极/漏极区域的下方部分的部分，其中第一对STI区域被分隔开并邻接半导体条带。 第一对STI区域还具有第一顶面。 第二对STI区域包括直接位于栅极电极下方的部分，其中第二对STI区域彼此分离并邻接半导体条带。 第二对STI区域具有高于第一顶表面的第二顶表面。

公开(公告)号：US20110121406A1

公开(公告)日：2011-05-26

申请号：US12871655

申请日：2010-08-30

Applicant: Tsung-Lin Lee ,  Chih Cheih Yeh ,  Chang-Yun Chang ,  Feng Yuan

Inventor： Tsung-Lin Lee ,  Chih Cheih Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L21/823431 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract translation: 集成电路结构包括包括第一器件区域中的第一部分和第二器件区域中的第二部分的半导体衬底。 第一半导体鳍片在半导体衬底之上并且具有第一鳍片高度。 第二半导体鳍片在半导体衬底之上并且具有第二鳍片高度。 第一鳍高度大于第二翅片高度。

公开(公告)号：US20110115024A1

公开(公告)日：2011-05-19

申请号：US12856343

申请日：2010-08-13

Applicant: Tsung-Lin Lee ,  Shao-Ming Yu

Inventor： Tsung-Lin Lee ,  Shao-Ming Yu

IPC: H01L27/088 ,  H01L21/302 ,  H01L21/28

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L27/088 ,  H01L27/0886

Abstract: In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc.

Abstract translation: 根据实施例，半导体器件包括至少三个有效区域。 至少三个活动区域是接近的。 所述至少三个有效区域的纵轴是平行的，并且所述至少三个有效区域中的每一个包括与相应有效区域的纵向轴线相交的边缘。 至少三个活动区域的边缘形成弧。

公开(公告)号：US20110089526A1

公开(公告)日：2011-04-21

申请号：US12838264

申请日：2010-07-16

Applicant: Tsung-Lin Lee ,  Chang-Yun Chang

Inventor： Tsung-Lin Lee ,  Chang-Yun Chang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/762 ,  H01L21/76232

Abstract: A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.

Abstract translation: 提供了一种用于在集成电路的衬底上形成多凹槽浅沟槽隔离结构的系统和方法。 集成电路包括衬底，在衬底中形成的至少两个浅沟槽隔离（STI）结构，设置在至少两个STI结构中的氧化物填充物，以及设置在至少两个STI结构中的氧化物填充物上的半导体器件。 第一STI结构形成为第一深度，并且第二STI结构形成为第二深度。 氧化物填充物填充至少两个STI结构，并且第一深度和第二深度基于设置在其上的半导体器件的半导体器件特性。

公开(公告)号：US20110008956A1

公开(公告)日：2011-01-13

申请号：US12610282

申请日：2009-10-31

Applicant: Tsung-Lin Lee ,  Clement Hsingjen Wann ,  Ching-Yu Chang

Inventor： Tsung-Lin Lee ,  Clement Hsingjen Wann ,  Ching-Yu Chang

IPC: H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature.

Abstract translation: 提供一种制造半导体器件的方法，其包括提供衬底。 材料层形成在衬底上。 聚合物层形成在材料层上。 使用聚合物层的一部分自组装纳米尺寸的特征。 使用纳米尺寸的特征对衬底进行图案化。

公开(公告)号：US20100136779A1

公开(公告)日：2010-06-03

申请号：US12648598

申请日：2009-12-29

Applicant: Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L21/28

CPC classification number: H01L29/7923 ,  H01L21/28282 ,  H01L29/4234

Abstract: A SONOS gate structure has an oxide structure on a substrate having gate pattern thereon. The oxide structure has a relatively thinner oxide portion on the substrate for keeping good program/erase efficiency, and a relatively thicker oxide portion on sidewalls of the gate pattern for inhibiting gate disturb. Trapping dielectric spacers are on formed the oxide structure laterally adjacent to said sidewalls of said gate pattern respectively.

Abstract translation: SONOS栅极结构在其上具有栅极图案的衬底上具有氧化物结构。 氧化物结构在衬底上具有相对较薄的氧化物部分，用于保持良好的编程/擦除效率，并且在用于抑制栅极干扰的栅极图案的侧壁上的相对较厚的氧化物部分。 捕获电介质间隔物分别形成在与所述栅极图案的所述侧壁相邻的氧化物结构上。

公开(公告)号：US07482236B2

公开(公告)日：2009-01-27

申请号：US11602809

申请日：2006-11-21

Applicant: Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L21/8234

CPC classification number: H01L29/4983 ,  H01L21/28282 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/792 ,  H01L29/7923 ,  Y10S438/954

Abstract: A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate. A top oxide material is deposited over the substrate. A silicon nitride spacer material is deposited over the top oxide material. Portions of the top oxide material and the silicon nitride spacer material are removed to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material. Source/drain regions are formed in the substrate.

Abstract translation: 栅极堆叠形成在基板上。 栅极堆叠具有侧壁。 氧化物 - 氮化物 - 氧化物材料沉积在栅极叠层上。 除去氧化物 - 氮化物 - 氧化物材料的一部分以形成氧化物 - 氧化物 - 氧化物结构。 氧化物 - 氧化物 - 氧化物结构具有通常为L形的横截面，沿着栅极叠层侧壁的至少一部分和沿着衬底的水平部分具有垂直部分。 顶部氧化物材料沉积在衬底上。 在顶部氧化物材料上沉积氮化硅间隔物材料。 除去顶部氧化物材料和氮化硅间隔物材料的部分以形成通过顶部氧化物材料从氧化物 - 氮化物 - 氧化物堆叠体分离的氮化硅间隔物。 源极/漏极区域形成在衬底中。

公开(公告)号：US20080296702A1

公开(公告)日：2008-12-04

申请号：US11807652

申请日：2007-05-30

Applicant: Tsung-Lin Lee ,  Chang-Yun Chang ,  Sheng-Da Liu ,  Fu-Liang Yang

Inventor： Tsung-Lin Lee ,  Chang-Yun Chang ,  Sheng-Da Liu ,  Fu-Liang Yang

IPC: H01L29/76

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space.

Abstract translation: 半导体结构包括半导体衬底; 以及在半导体衬底的表面处的第一Fin场效应晶体管（FinFET）和第二FinFET。 第一个FinFET包括第一个鳍; 以及在第一鳍的顶表面和侧壁上的第一栅电极。 第二FinFET包括通过鳍片空间与第一鳍片间隔开的第二鳍片; 以及在第二鳍的顶表面和侧壁上的第二栅电极。 第二栅电极与第一栅电极电断开。 第一和第二栅电极具有大于翅片空间的约一半的栅极高度。

公开(公告)号：US07292650B2

公开(公告)日：2007-11-06

申请号：US10609496

申请日：2003-07-01

Applicant: Tsung-Lin Lee ,  Rong-Liang Chiou

Inventor： Tsung-Lin Lee ,  Rong-Liang Chiou

IPC: H03M13/00 ,  H03K9/00 ,  H04L27/06

CPC classification number: H04L25/067 ,  H04L1/0054 ,  H04L1/0071 ,  H04L5/0007 ,  H04L5/006 ,  H04L5/0091 ,  H04L27/38

Abstract: A metric generation scheme for use in OFDM receivers. In a preferred embodiment, an OFDM receiver of the invention includes a dynamic quantizer to compress a series of channel-state information values. Also, a bit de-interleaver is provided to de-interleave a series of symbol-based data inverse to interleaving operations at a transmitter end. The de-interleaved symbol-based data is further compressed by another dynamic quantizer to yield a complex signal according to a constellation scheme. Then a metric generator calculates a bit metric of a zero group and a bit metric of a one group for each received bit in which the constellation is divided into the one group and the zero group for each bit location.

Abstract translation: 用于OFDM接收机的度量生成方案。 在优选实施例中，本发明的OFDM接收机包括用于压缩一系列信道状态信息值的动态量化器。 此外，提供了一个解交织器，用于将一系列基于符号的数据逆交换到发送器端处的交织操作。 解交织的基于符号的数据被另一个动态量化器进一步压缩，以产生根据星座图方案的复信号。 然后，度量发生器为每个接收的比特计算零组的比特量度和一组的比特度量，其中星座被划分成一个组，并且对于每个比特位置分配零组。

公开(公告)号：US20070145465A1

公开(公告)日：2007-06-28

申请号：US11313790

申请日：2005-12-22

Applicant: Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

Inventor： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

IPC: H01L29/788

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L29/7881

Abstract: Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different from the first conductivity type is formed in the semiconductor substrate. A second region of the second conductivity type is formed in the semiconductor substrate spaced apart from the first region. A channel region connects the first and second regions for the conduction of charges. A dielectric layer is disposed on the channel region. A control gate is disposed on the dielectric layer. A tunnel dielectric layer is conformably formed on the semiconductor substrate and the control gate. Two charge storage dots are spaced apart from each other at opposing lateral edges of the sidewalls of the control gate and surface of the semiconductor substrate.

Abstract translation: 具有多晶硅存储点的非易失性浮动栅极存储单元及其制造方法。 非易失性浮动栅极存储单元包括第一导电类型的半导体衬底。 在半导体衬底中形成不同于第一导电类型的第二导电类型的第一区域。 第二导电类型的第二区域形成在与第一区域间隔开的半导体衬底中。 通道区域连接第一和第二区域用于电荷传导。 电介质层设置在沟道区上。 控制栅极设置在电介质层上。 在半导体衬底和控制栅上一致地形成隧道介电层。 两个电荷存储点在控制栅极的侧壁和半导体衬底的表面的相对侧边缘处彼此间隔开。