公开(公告)号：US20050224797A1

公开(公告)日：2005-10-13

申请号：US10816562

申请日：2004-04-01

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04

CPC classification number: H01L29/045 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

Abstract: A microelectronic device including a first substrate bonded to a second substrate. The first and second substrate may have different crystallographic orientations. The first substrate includes an opening through which an epitaxially grown portion of the second substrate extends. A first semiconductor device is coupled to the first substrate. A second semiconductor device is coupled to the epitaxially grown portion of the second substrate.

Abstract translation: 一种微电子器件，包括接合到第二衬底的第一衬底。 第一和第二基底可以具有不同的晶体取向。 第一衬底包括第二衬底的外延生长部分延伸通过的开口。 第一半导体器件耦合到第一衬底。 第二半导体器件耦合到第二衬底的外延生长部分。

公开(公告)号：US06949443B2

公开(公告)日：2005-09-27

申请号：US10683901

申请日：2003-10-10

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/80

CPC classification number: H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7842

Abstract: A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

Abstract translation: 公开了一种改进的驱动电流的高性能半导体器件及其制造方法。 半导体器件具有构建在有源区上的源极和漏极区域，器件的长度与其宽度不同。 在有源区周围制造一个或多个隔离区域，然后用退火处理后其体积收缩率超过0.5％的预定隔离材料填充隔离区域。 在有源区上形成栅电极，并且在栅电极旁边形成一个或多个电介质间隔物。 然后，接触蚀刻停止层放置在器件上，其中隔离区，间隔物和接触蚀刻层有助于调制施加在有源区上的净应变，以便改善驱动电流。

公开(公告)号：US20050170594A1

公开(公告)日：2005-08-04

申请号：US11093847

申请日：2005-03-30

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/165 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract translation: 具有晶格失配区的应变通道晶体管结构及其制造方法。 晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极 区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，该区域和漏极区域包括具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。

公开(公告)号：US06921913B2

公开(公告)日：2005-07-26

申请号：US10379033

申请日：2003-03-04

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/165 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract translation: 具有晶格失配区的应变通道晶体管结构及其制造方法。 晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极 区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，其包含具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。

公开(公告)号：US20050079677A1

公开(公告)日：2005-04-14

申请号：US10683901

申请日：2003-10-10

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/80

CPC classification number: H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7842

Abstract: A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

公开(公告)号：US20050045949A1

公开(公告)日：2005-03-03

申请号：US10650445

申请日：2003-08-28

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L29/45 ,  H01L29/68 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/78618 ,  H01L29/78654

Abstract: A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).

Abstract translation: 一种半导体器件（100），包括位于衬底（110）上方并与衬底（110）成一体并具有第一侧壁（230）的电介质基座（220），位于电介质基座（220）上方的通道区域（210） （240），以及与沟道区（210）相对并且每个基本跨越第二侧壁（240）中的一个的源极和漏极区（410）。 还公开了结合半导体器件（100）的集成电路（800），以及制造半导体器件（100）的方法。

公开(公告)号：US20050035470A1

公开(公告)日：2005-02-17

申请号：US10639170

申请日：2003-08-12

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/8238 ,  H01L27/088

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

Abstract translation: 晶体管包括覆盖沟道区的栅极电介质。 源极区域和漏极区域位于沟道区域的相对侧上。 沟道区由第一半导体材料形成，源极和漏极区由第二半导体材料形成。 栅极电极覆盖栅极电介质。 在栅电极的侧壁上形成一对间隔物。 每个间隔件包括邻近通道区域的空隙。 高应力膜可以覆盖栅电极和间隔物。

公开(公告)号：US20050035426A1

公开(公告)日：2005-02-17

申请号：US10687377

申请日：2003-10-16

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Chung-Hu Ge ,  Wen-Chin Lee

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/00 ,  H01L21/8238

CPC classification number: H01L21/28123 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/7833

Abstract: A semiconductor isolation trench includes a substrate and a trench formed therein. The trench is lined with a nitrogen-containing liner and filled with a dielectric material. The nitrogen-containing liner preferably contacts the active region of a device, such as a transistor, located adjacent to the trench.

公开(公告)号：US20050032321A1

公开(公告)日：2005-02-10

申请号：US10637351

申请日：2003-08-08

Applicant: Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

Inventor： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos Diaz ,  Fu-Liang Yang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

Abstract: A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

Abstract translation: 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

公开(公告)号：US20050023576A1

公开(公告)日：2005-02-03

申请号：US10657616

申请日：2003-09-08

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC classification number: H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76232 ,  H01L21/823412 ,  H01L29/1054 ,  H01L29/66651

Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

Abstract translation: 包括适用于制造应变通道晶体管的高应变选择性外延顶层的半导体结构。 顶层沉积在一系列一个或多个下层的最上面。 每个层的晶格与其下层的晶格不匹配，其量不小于该系列的最低层与其所在的衬底之间的晶格失配。 沟槽形成在最上层的层中。 沟槽具有圆角，使得填充沟槽的电介质材料符合圆角。 通过在沟槽形成之后加热最上面的串联层来产生圆角。