公开(公告)号：US20190243772A1

公开(公告)日：2019-08-08

申请号：US15891322

申请日：2018-02-07

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Elliot H. Mednick

IPC: G06F12/0895 ,  G06F12/06 ,  G06F3/06

CPC classification number: G06F12/0895 ,  G06F3/0619 ,  G06F12/0646

Abstract: A method includes, for each data value in a set of one or more data values, determining a boundary between a high order portion of the data value and a low order portion of the data value, storing the low order portion at a first memory location utilizing a low data fidelity storage scheme, and storing the high order portion at a second memory location utilizing a high data fidelity storage scheme for recording data at a higher data fidelity than the low data fidelity storage scheme.

公开(公告)号：US10365996B2

公开(公告)日：2019-07-30

申请号：US15331270

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Gupta ,  David A. Roberts ,  Mitesh R. Meswani ,  Vilas Sridharan ,  Steven Raasch ,  Daniel I. Lowell

IPC: G06F12/00 ,  G06F12/02

Abstract: Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). A memory unit is selected for the data block for which the determined cost is the lowest, out of all memory units considered, and the data block is placed into that memory unit.

公开(公告)号：US20190042313A1

公开(公告)日：2019-02-07

申请号：US15974014

申请日：2018-05-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel ,  David A. Roberts

IPC: G06F9/50 ,  G06F9/52

Abstract: Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of processing resources of the first FPGA. Later, the system detects a release of the portion of the processing resources on the first FPGA by the first user process. Then, the system receives a second request to allocate the first FPGA from a second user process. In response to the second request, the system maps the first FPGA into an address space of the second user process.

公开(公告)号：US10185498B2

公开(公告)日：2019-01-22

申请号：US15184996

申请日：2016-06-16

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F3/06

Abstract: A memory system includes a write buffer, a main memory having a higher latency than the write buffer, and a memory controller. In response to a write request indicating first data for storing at a write address in the main memory, the memory controller adds a new write entry in the write buffer, where the new write entry includes the write address and the first data, and updates a pointer of a previous write entry in the write buffer to point to the new write entry. In response to a write-back instruction, the memory controller traverses a plurality of write entries stored in the write buffer, and writes into the main memory second data of the previous write entry and the first data of the new write entry.

公开(公告)号：US10164639B1

公开(公告)日：2018-12-25

申请号：US15812411

申请日：2017-11-14

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Andrew G. Kegel ,  Elliot H. Mednick

IPC: H03K19/177 ,  G06F17/50 ,  G06F15/78

Abstract: A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.

公开(公告)号：US20180181492A1

公开(公告)日：2018-06-28

申请号：US15389573

申请日：2016-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Gupta ,  Vilas Sridharan ,  David A. Roberts

IPC: G06F12/0891

CPC classification number: G06F11/34 ,  G06F12/0891 ,  G06F12/12 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/60

Abstract: Described herein are waterfall counters and an application to architectural vulnerability factor (AVF) estimation. Waterfall counters count events that are generated at event generation logic. The waterfall counters are a combination of small, fast counters local to the event generation logic, and larger, global counters in fast memory. The local counters can be saturation or oscillation counters. When a local counter is saturated or evicted, the value from the local counter is added to the global counter. This addition can be done using logic local to the local or global counter. The waterfall counters provide a full-accuracy event count without the high bandwidth that is needed to maintain the global counters. An AVF estimation can be determined based on ratios from counts of read events, write events, and total events using the waterfall counters.

公开(公告)号：US09767028B2

公开(公告)日：2017-09-19

申请号：US14928981

申请日：2015-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin Y. Cheng ,  David A. Roberts

IPC: G06F12/00 ,  G06F12/0862 ,  G06F13/42

CPC classification number: G06F12/0862 ,  G06F9/4401 ,  G06F13/42 ,  G06F15/7821 ,  G06F2212/1024 ,  G06F2212/45

Abstract: Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.

公开(公告)号：US20170200672A1

公开(公告)日：2017-07-13

申请号：US14995002

申请日：2016-01-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  David A. Roberts

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.

公开(公告)号：US20170123670A1

公开(公告)日：2017-05-04

申请号：US14924881

申请日：2015-10-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan Jayasena ,  David A. Roberts

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/061 ,  G06F3/067 ,  G06F12/08 ,  G06F12/0822 ,  G06F13/16

Abstract: A memory-to-memory copy operation control system includes a processor configured to receive an instruction to perform a memory-to-memory copy operation and a memory module network in communication with the processor. The memory module network has a plurality of memory modules that include a proximal memory module in direct communication with the processor and one or more additional memory modules in communication with the processor via the proximal memory module. The system also includes a memory controller in communication with the processor and the network of memory modules. The processor is configured to issue a first command causing data to be copied from a first memory module to a second memory module without sending the data to the processor or the memory controller.

公开(公告)号：US20170048358A1

公开(公告)日：2017-02-16

申请号：US15138485

申请日：2016-04-26

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Kevin Y. Cheng ,  Nathan Hu

IPC: H04L29/06 ,  H04L12/741

CPC classification number: H04L69/04 ,  G06F9/00 ,  G06F13/00 ,  H04L45/74

Abstract: Systems, apparatuses, and methods for reducing inter-node bandwidth are contemplated. A computer system includes requesting nodes sending transactions to target nodes. A requesting node sends a packet that includes a register identifier (ID) in place of a data value in the packet. The register ID indicates a register in the target node storing the data value. The register ID uses fewer bits in the packet than the data value. The data value may be a memory address referencing a memory location in the target node. The received packet may also include an opcode indicating an operation to perform on the targeted data value.

Abstract translation: 考虑了用于减少节点间带宽的系统，装置和方法。 计算机系统包括请求节点向目标节点发送事务。 请求节点发送包含寄存器标识符（ID）的数据包，代替数据包中的数据值。 寄存器ID表示存储数据值的目标节点中的寄存器。 寄存器ID在数据包中使用的数据比数据值少。 数据值可以是引用目标节点中的存储器位置的存储器地址。 所接收的分组还可以包括指示针对目标数据值执行的操作的操作码。