公开(公告)号：US20130337583A1

公开(公告)日：2013-12-19

申请号：US13901341

申请日：2013-05-23

Applicant: ASM IP Holding B.V.

Inventor： Akiko Kobayashi ,  Yosuke Kimura ,  Dai Ishikawa ,  Kiyohiro Matsushita

IPC: H01L21/768

CPC classification number: H01L21/76825 ,  C23C16/045 ,  C23C16/45527 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

Abstract: A method for repairing process-related damage of a dielectric film includes: (i) adsorbing a first gas containing silicon on a surface of the damaged dielectric film without depositing a film in the absence of reactive species, (ii) adsorbing a second gas containing silicon on a surface of the dielectric film, followed by applying reactive species to the surface of the dielectric film, to form a monolayer film thereon, and (iii) repeating step (ii). The duration of exposing the surface to the first gas in step (i) is longer than the duration of exposing the surface to the second gas in step (ii).

Abstract translation: 一种用于修复电介质膜的工艺相关损伤的方法包括：（i）在不存在反应性物质的情况下，在不沉积膜的情况下，在损坏的电介质膜的表面上吸附含硅的第一气体，（ii）吸附含有 在电介质膜的表面上形成硅，然后在电介质膜的表面上施加反应性物质，以在其上形成单层膜，和（iii）重复步骤（ii）。 在步骤（i）中将表面暴露于第一气体的持续时间比在步骤（ii）中将表面暴露于第二气体的持续时间长。

公开(公告)号：US11676812B2

公开(公告)日：2023-06-13

申请号：US16904166

申请日：2020-06-17

Applicant: ASM IP Holding B.V.

Inventor： Dai Ishikawa ,  Atsuki Fukazawa ,  Eiichiro Shiba ,  Shinya Ueda ,  Taishi Ebisudani ,  SeungJu Chun ,  YongMin Yoo ,  YoonKi Min ,  SeYong Kim ,  JongWan Choi

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/0217 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31111 ,  H01J2237/3347

Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.

公开(公告)号：US10910262B2

公开(公告)日：2021-02-02

申请号：US15815483

申请日：2017-11-16

Applicant: ASM IP Holding B.V.

Inventor： Aurélie Kuroda ,  Akiko Kobayashi ,  Dai Ishikawa

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285

Abstract: A method of selectively depositing a capping layer structure on a semiconductor device structure is disclosure. The method may include; providing a partially fabricated semiconductor device structure comprising a surface including a metallic interconnect material, a metallic barrier material, and a dielectric material. The method may also include; selectively depositing a first metallic capping layer over the metallic barrier material and over the metallic interconnect material relative to the dielectric material; and selectively depositing a second metallic capping layer over the first metallic capping layer relative to the dielectric material. Semiconductor device structures including a capping layer structure are also disclosed.

公开(公告)号：US20200291511A1

公开(公告)日：2020-09-17

申请号：US16676017

申请日：2019-11-06

Applicant: ASM IP Holding B.V.

Inventor： Delphine Longrie ,  Antti Juhani Niskanen ,  Han Wang ,  Qi Xie ,  Jan Willem Maes ,  Shang Chen ,  Toshiharu Watarai ,  Takahiro Onuma ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: C23C16/02 ,  C23C16/06 ,  C23C16/34 ,  C23C16/44 ,  C23C16/455 ,  C23C16/56 ,  H01L21/768 ,  H01L21/285

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US10480064B2

公开(公告)日：2019-11-19

申请号：US16040844

申请日：2018-07-20

Applicant: ASM IP Holding B.V.

Inventor： Delphine Longrie ,  Antti Juhani Niskanen ,  Han Wang ,  Qi Xie ,  Jan Willem Maes ,  Shang Chen ,  Toshiharu Watarai ,  Takahiro Onuma ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: C23C16/02 ,  C23C16/455 ,  H01L21/285 ,  H01L21/768 ,  C23C16/06 ,  C23C16/34 ,  C23C16/44 ,  C23C16/56

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US20190057857A1

公开(公告)日：2019-02-21

申请号：US16167225

申请日：2018-10-22

Applicant: ASM IP Holding B.V.

Inventor： Dai Ishikawa ,  Atsuki Fukazawa ,  Eiichiro Shiba ,  Shinya Ueda ,  Taishi Ebisudani ,  SeungJu Chun ,  YongMin Yoo ,  YoonKi Min ,  SeYong Kim ,  JongWan Choi

IPC: H01L21/02 ,  H01L21/311

Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.

公开(公告)号：US20190055643A1

公开(公告)日：2019-02-21

申请号：US16040844

申请日：2018-07-20

Applicant: ASM IP Holding B.V.

Inventor： Delphine Longrie ,  Antti Juhani Niskanen ,  Han Wang ,  Qi Xie ,  Jan Willem Maes ,  Shang Chen ,  Toshiharu Watarai ,  Takahiro Onuma ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: C23C16/02 ,  C23C16/44 ,  C23C16/06 ,  H01L21/768 ,  C23C16/455 ,  H01L21/285 ,  C23C16/56 ,  C23C16/34

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US20180080121A1

公开(公告)日：2018-03-22

申请号：US15795768

申请日：2017-10-27

Applicant: ASM IP Holding B.V.

Inventor： Delphine Longrie ,  Antti Juhani Niskanen ,  Han Wang ,  Qi Xie ,  Jan Willem Maes ,  Shang Chen ,  Toshiharu Watarai ,  Takahiro Onuma ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: C23C16/02 ,  C23C16/455 ,  H01L21/768 ,  H01L21/285

CPC classification number: C23C16/02 ,  C23C16/06 ,  C23C16/345 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45525 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28562 ,  H01L21/7685

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US09803277B1

公开(公告)日：2017-10-31

申请号：US15177195

申请日：2016-06-08

Applicant: ASM IP Holding B.V.

Inventor： Delphine Longrie ,  Antti Juhani Niskanen ,  Han Wang ,  Qi Xie ,  Jan Willem Maes ,  Shang Chen ,  Toshiharu Watarai ,  Takahiro Onuma ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: C23C16/02 ,  H01L21/768 ,  H01L21/285 ,  C23C16/455

CPC classification number: C23C16/02 ,  C23C16/06 ,  C23C16/345 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45525 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28562 ,  H01L21/7685

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US09353441B2

公开(公告)日：2016-05-31

申请号：US13646403

申请日：2012-10-05

Applicant: ASM IP Holding B.V.

Inventor： Hsiao Pei Chung ,  Hirofumi Arai ,  Dai Ishikawa

IPC: C23C16/50 ,  C23C16/00 ,  C23F1/00 ,  H01L21/306 ,  C23C16/458 ,  H01L21/67 ,  H01J37/32 ,  F27D5/00

CPC classification number: C23C16/4586 ,  F27D5/0037 ,  H01J37/32724 ,  H01L21/67109

Abstract: A pedestal for supporting a substrate includes: a heating plate for heating the substrate; an upper cooling plate for cooling the substrate, installed on the heating plate and provided with an upper fluid path for passing a cooling fluid therethrough; and an lower cooling plate for cooling the substrate, installed under the heating plate and including a lower fluid path for passing a cooling fluid therethrough.

Abstract translation: 用于支撑基板的基座包括：用于加热基板的加热板; 用于冷却基板的上部冷却板，安装在加热板上并设置有用于使冷却流体通过的上部流体路径; 以及用于冷却基板的下部冷却板，安装在加热板下方并且包括用于使冷却流体从其中通过的下部流体路径。