-
公开(公告)号：US20170213557A1
公开(公告)日：2017-07-27
申请号：US15482142
申请日：2017-04-07
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
-
公开(公告)号：US09529405B2
公开(公告)日：2016-12-27
申请号：US14459482
申请日：2014-08-14
Applicant: Apple Inc.
Inventor： Erik P. Machnicki , Gilbert H. Herbeck , Shu-Yi Yu , Sebastian Skalberg
IPC: G06F1/32
CPC classification number: G06F1/3237 , G06F1/3228 , G06F1/324 , G06F1/3287 , Y02D10/128 , Y02D10/171 , Y02D50/20
Abstract: A system and method for managing idleness of functional units in an IC is disclosed. An IC includes a subsystem having a number of functional units and an idle aggregation unit. When a particular functional unit determines that it is idle, it may assert an idle indication to the idle aggregation unit. When the respective idle indications are concurrently asserted for all of the functional units, the idle aggregation unit may assert and provide respective idle request signals to each of the functional units. Responsive to receiving an idle request unit, a given functional unit may provide an acknowledgement signal to the idle aggregation unit if no transactions are incoming. If all functional units have concurrently asserted their respective acknowledgement signals, the idle aggregation unit may provide an indication of the same to a clock gating unit, which may then gate the clock signal(s) received by the functional units.
Abstract translation: 公开了一种用于管理IC中的功能单元的空闲的系统和方法。 IC包括具有多个功能单元和空闲聚合单元的子系统。 当特定功能单元确定它是空闲时，它可以向空闲聚合单元断言空闲指示。 当对于所有功能单元同时断言相应的空闲指示时，空闲汇聚单元可以向每个功能单元断言并提供相应的空闲请求信号。 响应于接收空闲请求单元，如果没有事务进入，则给定功能单元可以向空闲聚合单元提供确认信号。 如果所有功能单元已经同时确定其各自的确认信号，则空闲聚合单元可以向时钟选通单元提供相同的指示，时钟门控单元然后可以对由功能单元接收的时钟信号进行门控。
-
公开(公告)号：US09413361B1
公开(公告)日：2016-08-09
申请号：US14608107
申请日：2015-01-28
Applicant: Apple Inc.
Inventor： Gilbert H. Herbeck
CPC classification number: H03L7/0802 , G06F1/04 , G06F1/08 , G06F1/324
Abstract: A system may include a processor, a first clock source generating a first clock signal, a second clock source generating a second clock signal, and a clock generation unit. In a first closed-loop mode of operation, the clock generation unit may be configured to generate a system clock signal at a target frequency by comparing the system clock signal to the first clock signal. The clock generation unit may be configured to generate the system clock signal in an open-loop mode of operation in response to a transition in a control signal. The clock generation unit may be configured to operate in a second closed-loop mode of operation after operating in the open-loop mode of operation, wherein the clock generation unit is configured to generate the system clock signal at substantially the same target frequency by comparing the system clock signal to the second clock signal.
Abstract translation: 系统可以包括处理器，产生第一时钟信号的第一时钟源，产生第二时钟信号的第二时钟源和时钟产生单元。 在第一闭环操作模式中，时钟生成单元可以被配置为通过将系统时钟信号与第一时钟信号进行比较来产生目标频率的系统时钟信号。 时钟生成单元可以被配置为响应于控制信号中的转变而以开环操作模式生成系统时钟信号。 时钟生成单元可以被配置为在开环操作模式下操作之后以第二闭环操作模式操作，其中时钟生成单元被配置为通过比较产生基本上相同的目标频率的系统时钟信号 系统时钟信号到第二个时钟信号。
-
公开(公告)号：US09367081B2
公开(公告)日：2016-06-14
申请号：US14489380
申请日：2014-09-17
Applicant: Apple Inc.
Inventor： Gilbert H. Herbeck , Shane J. Keil
CPC classification number: G06F1/12
Abstract: An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal.
Abstract translation: 公开了一种用于同步两个时钟信号的装置。 该装置可以包括选择单元和电路。 选择单元可以被配置为选择第一或第二时钟信号作为输出时钟信号。 第一时钟信号的频率可能小于第二时钟信号的频率。 电路可以被配置为向选择单元发送第一信号，使得选择单元选择第一时钟信号。 电路还可以被配置为向选择单元发送第二信号，使得选择单元选择第二时钟信号的时钟脉冲的子集作为输出时钟信号。 第二时钟信号的时钟脉冲的子集可以包括对应于第一时钟信号的转变的第二时钟信号的时钟脉冲。
-
公开(公告)号：US20160077546A1
公开(公告)日：2016-03-17
申请号：US14489380
申请日：2014-09-17
Applicant: Apple Inc.
Inventor： Gilbert H. Herbeck , Shane J. Keil
IPC: G06F1/12
CPC classification number: G06F1/12
Abstract: An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal.
Abstract translation: 公开了一种用于同步两个时钟信号的装置。 该装置可以包括选择单元和电路。 选择单元可以被配置为选择第一或第二时钟信号作为输出时钟信号。 第一时钟信号的频率可以小于第二时钟信号的频率。 电路可以被配置为向选择单元发送第一信号，使得选择单元选择第一时钟信号。 电路还可以被配置为向选择单元发送第二信号，使得选择单元选择第二时钟信号的时钟脉冲的子集作为输出时钟信号。 第二时钟信号的时钟脉冲的子集可以包括对应于第一时钟信号的转变的第二时钟信号的时钟脉冲。
-
Patent Agency Ranking
公开(公告)号：US20140310443A1
公开(公告)日：2014-10-16
申请号：US13861136
申请日：2013-04-11
Applicant: APPLE INC.
Inventor： Gilbert H. Herbeck
IPC: G06F13/28
Abstract: An interface unit configured to perform transfers between a processor and one or more peripheral devices is disclosed. A system includes a processor, a number of devices (e.g., peripheral devices), and an interface unit coupled therebetween. The interface unit includes FIFOs for storing data transmitted to or received from the devices by the processor. The interface unit may access data from a device responsive to a request from the processor. The data may be loaded into a FIFO according to transfer parameters controlled by the device. After the data has been received by the FIFO, the interface unit may generate an interrupt to the processor. Data may then be transferred from the interface unit to the processor according to transfer parameters controlled by the processor. The interface unit may thus homogenize a processor interface to a number of different devices.
Abstract translation: 公开了一种被配置为在处理器和一个或多个外围设备之间执行传送的接口单元。 系统包括处理器，多个设备（例如，外围设备）以及耦合在其间的接口单元。 接口单元包括用于存储由处理器发送到设备或从设备接收的数据的FIFO。 接口单元可以响应于来自处理器的请求来访问来自设备的数据。 数据可以根据由设备控制的传输参数加载到FIFO中。 在FIFO接收到数据之后，接口单元可能会向处理器产生中断。 然后可以根据由处理器控制的传送参数将数据从接口单元传送到处理器。 因此，接口单元可以将处理器接口均匀化到多个不同的设备。
-
公开(公告)号：US10243990B1
公开(公告)日：2019-03-26
申请号：US15275044
申请日：2016-09-23
Applicant: Apple Inc.
Inventor： Zhimin Chen , Timothy R. Paaske , Gilbert H. Herbeck
Abstract: A system and method for detecting replay attacks on secure data are disclosed. A system on a chip (SOC) includes a security processor. Blocks of data corresponding to sensitive information are stored in off-chip memory. The security processor uses an integrity data structure, such as an integrity tree, for the blocks. The intermediate nodes of the integrity tree use nonces which have been generated independent of any value within a corresponding block. By using only the nonces to generate tags in the root at the top layer stored in on-chip memory and the nodes of the intermediate layers stored in off-chip memory, an amount of storage used is reduced for supporting the integrity tree. When the security processor detects events which create access requests for one or more blocks, the security processor uses the integrity tree to verify a replay attack has not occurred and corrupted data.
-
公开(公告)号：US09928838B2
公开(公告)日：2018-03-27
申请号：US15482142
申请日：2017-04-07
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
-
39.发明申请公开(公告)号：US20170177256A1
公开(公告)日：2017-06-22
申请号：US15447328
申请日：2017-03-02
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
-
公开(公告)号：US20170168520A1
公开(公告)日：2017-06-15
申请号：US14965073
申请日：2015-12-10
Applicant: Apple Inc.
Inventor： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC: G06F1/12
Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.
-
-
-
-
-
-
-
-
-
Search Results
46
records
(took 0.017 seconds)
