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    Serial data receiver with even/odd mismatch compensation
    31.
    发明授权
    Serial data receiver with even/odd mismatch compensation 有权

    公开(公告)号：US12244683B2

    公开(公告)日：2025-03-04

    申请号：US18319421

    申请日：2023-05-17

    Applicant: Apple Inc.

    Inventor： Ryan D. Bartling ,  Jafar Savoj

    IPC: H04L23/02 ,  H04B1/04 ,  H04L7/00 ,  H04L7/033

    Abstract: A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The sample circuit may sample a serial data stream at different times that correspond to even-numbered and odd-numbered symbols in the serial data stream. The recovery circuit may use different coefficients to process the respective samples of the even-numbered and odd-numbered symbols in order to recover the data symbols encoded in the serial data stream.

    Serial receiver circuit with follower skew adaptation
    32.
    发明授权
    Serial receiver circuit with follower skew adaptation 有权

    公开(公告)号：US12052335B2

    公开(公告)日：2024-07-30

    申请号：US18161995

    申请日：2023-01-31

    Applicant: Apple Inc.

    Inventor： Ryan D. Bartling ,  Jafar Savoj

    IPC: H04L7/033 ,  H04L7/00 ,  H04L7/02

    CPC classification number: H04L7/0058 ,  H04L7/0062 ,  H04L7/02 ,  H04L7/0066

    Abstract: A serial data receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. During startup of a communication channel, phase information generated by the analog receiver circuit may be used to generate clock signals for the ADC-based receiver circuit. After a period of time, the ADC-based receiver circuit can generate its own phase information to be used in the generation of the clock signals.

    Receiver with Feed Forward Equalization
    33.
    发明公开
    Receiver with Feed Forward Equalization 审中-公开

    公开(公告)号：US20240089154A1

    公开(公告)日：2024-03-14

    申请号：US17931096

    申请日：2022-09-09

    Applicant: Apple Inc.

    Inventor： Bo Sun ,  Jafar Savoj

    IPC: H04L25/03 ,  H04L7/00

    CPC classification number: H04L25/03038 ,  H04L7/0016

    Abstract: A receiver with feed-forward equalization is disclosed. A receiver includes a delay circuit configured to receive a first signal that encodes a serial data stream having a plurality of data symbols. The delay circuit includes at least one T-coil circuit and is configured to generate a plurality of delayed signals using the first signal. The receiver further includes a front-end circuit configured to generate an equalized signal using the at first signal and one or more delayed signals of the plurality of delayed signals. A sample circuit is configured to sample the equalized signal to generate a plurality of samples. A recovery circuit configured to generate a plurality of recovered data symbols using the plurality of samples.

    Integration of Analog Circuits Inside Digital Blocks
    34.
    发明公开
    Integration of Analog Circuits Inside Digital Blocks 审中-公开

    公开(公告)号：US20240014821A1

    公开(公告)日：2024-01-11

    申请号：US18329027

    申请日：2023-06-05

    Applicant: Apple Inc.

    Inventor： Ramy A. Ahmed ,  Bruno W. Garlepp ,  Jafar Savoj

    IPC: H03K21/40 ,  H03K3/03 ,  H03K19/0175 ,  H03K21/08

    CPC classification number: H03K21/403 ,  H03K3/0315 ,  H03K19/017509 ,  H03K21/08

    Abstract: A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

    Hybrid serial receiver circuit
    35.
    发明授权
    Hybrid serial receiver circuit 有权

    公开(公告)号：US11689351B2

    公开(公告)日：2023-06-27

    申请号：US17482302

    申请日：2021-09-22

    Applicant: Apple Inc.

    Inventor： Ryan D. Bartling ,  Jafar Savoj ,  Brian S. Leibowitz

    IPC: H04L7/00 ,  H04L25/03

    CPC classification number: H04L7/0079 ,  H04L7/0016 ,  H04L25/03878

    Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.

    Latency Reduction in Analog-to-Digital Converter-Based Receiver Circuits
    36.
    发明申请
    Latency Reduction in Analog-to-Digital Converter-Based Receiver Circuits 有权

    公开(公告)号：US20230093114A1

    公开(公告)日：2023-03-23

    申请号：US17482322

    申请日：2021-09-22

    Applicant: Apple Inc.

    Inventor： Ryan D. Bartling ,  Jafar Savoj ,  Brian S. Leibowitz ,  Shah M. Sharif

    IPC: H03M1/06

    Abstract: A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.

    Reference circuit for metrology system
    37.
    发明授权
    Reference circuit for metrology system 有权

    公开(公告)号：US11022503B2

    公开(公告)日：2021-06-01

    申请号：US16735600

    申请日：2020-01-06

    Applicant: Apple Inc.

    Inventor： Daniel J. Fritchman ,  Jafar Savoj

    IPC: G01K17/00 ,  G01K7/20 ,  G01R31/26 ,  G01K15/00 ,  G01R19/00

    Abstract: Reference center circuitry for a metrology system is disclosed. In one embodiment, the circuitry includes a reference sensor having a topology and characteristics identical to a number of sensors throughout an IC. The both the reference sensor and the sensors on the IC may be used to perform voltage and temperature measurements. The reference sensor may receive a voltage from a precision voltage supply, and may be used as a sensor to provide a basis for calibrating the other sensors, as well. Thereafter, temperature readings obtained from the other sensors may be correlated to the readings obtained by the reference sensor for enhanced accuracy. The reference center circuitry also includes analog process monitoring circuitry, which may be coupled to some, if not all of the transistors implemented on an IC.

    Digital Sensor with Embedded Reference Clock
    38.
    发明申请
    Digital Sensor with Embedded Reference Clock 审中-公开

    公开(公告)号：US20190317547A1

    公开(公告)日：2019-10-17

    申请号：US15953019

    申请日：2018-04-13

    Applicant: Apple Inc.

    Inventor： Jafar Savoj ,  Amr A. Hafez ,  Ramy A. Ahmed

    IPC: G06F1/10 ,  G01K13/00 ,  G01R19/165 ,  H03K3/03 ,  G11C19/28

    Abstract: A sensor circuit and integrated circuit having the same is disclosed. In one embodiment, a sensor circuit includes first and second ring oscillators having different circuit topologies. A first counter is coupled to receive an output signal from the first ring oscillator, while a second counter is coupled to receive an output signal from the second ring oscillator. The sensor circuit further includes a local clock circuit that provides a clock signal to the first and second counters. Furthermore, the local clock circuit is coupled to provide the clock signal exclusively to circuitry within the sensor circuit, the circuitry including the first and second counters.

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