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    Address decoding circuitry
    35.
    发明授权
    Address decoding circuitry 有权

    公开(公告)号：US09691455B2

    公开(公告)日：2017-06-27

    申请号：US14796744

    申请日：2015-07-10

    Applicant: ARM Limited

    Inventor： Mudit Bhargava

    IPC: G11C8/00 ,  G11C8/10 ,  G11C8/18

    CPC classification number: G11C8/10 ,  G11C8/18

    Abstract: Various implementations described herein are directed to an integrated circuit for address decoding. The integrated circuit may include an input circuit configured to provide an encoded address via multiple address lines. The integrated circuit may include an address decoding circuit configured to directly translate the encoded address provided via the multiple address lines. The address decoding circuit may include multiple decoding blocks with each block having a first stage coupled to a second stage. The first stage of each block may include a first number of decoding transistors configured to decode first address bit values from the multiple address lines. The second stage of each block may include a second number of decoding transistors configured to decode second address data bit values from the multiple address lines. The integrated circuit may include an output circuit configured to provide a decoded address to a wordline driver circuit in memory.

    Methods and circuits of spatial alignment
    36.
    发明授权
    Methods and circuits of spatial alignment 有权

    公开(公告)号：US12223010B2

    公开(公告)日：2025-02-11

    申请号：US17339895

    申请日：2021-06-04

    Applicant: Arm Limited

    Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Saurabh Pijuskumar Sinha ,  Rahul Mathur

    IPC: G06F17/16 ,  G06F9/30

    Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.

    Memory for an artificial neural network accelerator
    37.
    发明授权
    Memory for an artificial neural network accelerator 有权

    公开(公告)号：US12086453B2

    公开(公告)日：2024-09-10

    申请号：US17103632

    申请日：2020-11-24

    Applicant: Arm Limited

    Inventor： Mudit Bhargava ,  Paul Nicholas Whatmough ,  Supreet Jeloka ,  Zhi-Gang Liu

    IPC: G11C16/04 ,  G06F3/06 ,  G06N3/063 ,  G11C11/54

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06N3/063 ,  G11C11/54

    Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of write word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each write word selector has an input port and a plurality of output ports, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the write word selectors of the first bank and the second bank, and configured to select a combination of write word selectors from at least one of the first bank and the second bank based on a bank select signal.

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