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77 条记录 (耗时 0.026 秒)

    Self-Aligned Contact For Replacement Gate Devices
    31.
    发明申请
    Self-Aligned Contact For Replacement Gate Devices 有权
    用于替代门装置的自对准触点

    公开(公告)号：US20120139061A1

    公开(公告)日：2012-06-07

    申请号：US12958607

    申请日：2010-12-02

    申请人： Ravikumar Ramachandran ,  Ying Li ,  Richard S. Wise

    发明人： Ravikumar Ramachandran ,  Ying Li ,  Richard S. Wise

    IPC分类号： H01L29/772 ,  H01L21/283

    CPC分类号： H01L29/78 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

    摘要： A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.

    摘要翻译： 替代栅极堆叠的导电顶表面通过至少一个蚀刻相对于平坦化介电层的顶表面凹陷。 介电覆盖层沉积在平坦化电介质层和替代栅极堆叠的顶表面上，使得替代栅极堆叠上的介电顶盖层的一部分的顶表面相对于上述电介质层的另一部分垂直凹陷 平坦化介电层。 电介质覆盖层的垂直偏移可以与选择性通孔蚀刻工艺结合使用以形成自对准接触结构。

    Dual metal and dual dielectric integration for metal high-k FETs
    32.
    发明授权
    Dual metal and dual dielectric integration for metal high-k FETs 有权
    金属高k FET的双金属和双电介质集成

    公开(公告)号：US07943457B2

    公开(公告)日：2011-05-17

    申请号：US12423236

    申请日：2009-04-14

    申请人： Michael P. Chudzik ,  Wiliam K. Henson ,  Rashmi Jha ,  Yue Liang ,  Ravikumar Ramachandran ,  Richard S. Wise

    发明人： Michael P. Chudzik ,  Wiliam K. Henson ,  Rashmi Jha ,  Yue Liang ,  Ravikumar Ramachandran ,  Richard S. Wise

    IPC分类号： H01L21/336

    CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/49 ,  H01L29/7833

    摘要： The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

    摘要翻译： 在一个实施例中，本发明提供一种形成半导体器件的方法，该半导体器件包括提供包括第一导电类型区域和第二导电类型区域的衬底; 在所述基板的第一导电类型区域和所述第二导电类型区域之上形成包括栅极电介质的栅极堆叠和覆盖所述高k栅极电介质的第一金属栅极导体; 去除存在于第一导电类型区域中的第一金属栅极导体的一部分以暴露存在于第一导电类型区域中的栅极电介质; 将氮基等离子体施加到所述基板，其中所述氮基等离子体氮化存在于所述第一导电类型区域中的所述栅极电介质，并且氮化所述第二导电类型区域中存在的所述第一金属栅极导体; 以及形成覆盖存在于第一导电类型区域中的至少栅极电介质的第二金属栅极导体。

    Vertical semiconductor devices
    36.
    发明授权
    Vertical semiconductor devices 失效
    垂直半导体器件

    公开(公告)号：US06887761B1

    公开(公告)日：2005-05-03

    申请号：US10708647

    申请日：2004-03-17

    申请人： Hiroyuki Akatsu ,  Thomas W. Dyer ,  Ravikumar Ramachandran ,  Kenneth T. Settlemyer, Jr.

    发明人： Hiroyuki Akatsu ,  Thomas W. Dyer ,  Ravikumar Ramachandran ,  Kenneth T. Settlemyer, Jr.

    IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L29/78 ,  H01I29/76

    CPC分类号： H01L29/66666 ,  H01L21/2257 ,  H01L21/76224 ,  H01L29/7827

    摘要： A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose semiconductor material has an orientation plane perpendicular to the surface of the substrate. Then, vertical transistors are formed around and along the depth of the deep trench. Next, two shallow trench isolation are formed such that they sandwich the deep trench in an active region and the two shallow trench isolation regions abut the active region via planes perpendicular to the orientation plane. Then, the channel regions of the vertical transistors are exposed to the atmosphere in the deep trench and then chemically etched to planes parallel to the orientation plane. Then, a gate dielectric layer is formed on the wall of the deep trench. Finally, the deep trench is filled with poly-silicon to form the gate for the vertical transistors.

    摘要翻译： 一种用于增加垂直半导体器件的阈值电压的方法和结构。 该方法包括在其半导体材料具有垂直于衬底表面的取向平面的衬底中形成深沟槽。 然后，在深沟槽的深度周围形成垂直晶体管。 接下来，形成两个浅沟槽隔离，使得它们在有源区域中夹住深沟槽，并且两个浅沟槽隔离区域经由垂直于取向平面的平面邻接有源区。 然后，垂直晶体管的沟道区域暴露在深沟槽中的大气中，然后化学蚀刻到平行于取向平面的平面上。 然后，在深沟槽的壁上形成栅极电介质层。 最后，深沟槽充满多晶硅，形成垂直晶体管的栅极。