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    Metal Gated Ultra Short MOSFET Devices
    31.
    发明申请
    Metal Gated Ultra Short MOSFET Devices 失效
    金属栅极超短MOSFET器件

    公开(公告)号：US20080124860A1

    公开(公告)日：2008-05-29

    申请号：US12013704

    申请日：2008-01-14

    申请人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

    发明人： Jack Oon Chu ,  Bruce B. Doris ,  Meikei Ieong ,  Jing Wang

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L29/7838 ,  H01L21/28017 ,  H01L29/105

    摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

    摘要翻译： 适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。 体层掺杂了与地平面相反的杂质。 栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。 栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。 在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

    High-performance CMOS devices on hybrid crystal oriented substrates
    32.
    发明授权
    High-performance CMOS devices on hybrid crystal oriented substrates 失效
    混合晶体取向基板上的高性能CMOS器件

    公开(公告)号：US07329923B2

    公开(公告)日：2008-02-12

    申请号：US10250241

    申请日：2003-06-17

    申请人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

    发明人： Bruce B. Doris ,  Kathryn W. Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey W. Sleight ,  Min Yang

    IPC分类号： H01L27/01

    CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

    摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

    摘要翻译： 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

    Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
    33.
    发明授权
    Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs 有权
    用于高迁移率平面和多栅极MOSFET的混合衬底技术

    公开(公告)号：US07291886B2

    公开(公告)日：2007-11-06

    申请号：US10872605

    申请日：2004-06-21

    申请人： Bruce B. Doris ,  Meikei Ieong ,  Edward J. Nowak ,  Min Yang

    发明人： Bruce B. Doris ,  Meikei Ieong ,  Edward J. Nowak ,  Min Yang

    IPC分类号： H01L27/01 ,  H01L27/12

    CPC分类号： H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

    摘要： A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

    摘要翻译： 提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。 混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。 由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。 本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

    Ultra-thin Si MOSFET device structure and method of manufacture
    34.
    发明授权
    Ultra-thin Si MOSFET device structure and method of manufacture 失效
    超薄Si MOSFET器件结构及制造方法

    公开(公告)号：US07247569B2

    公开(公告)日：2007-07-24

    申请号：US10725848

    申请日：2003-12-02

    申请人： Diane C. Boyd ,  Bruce B. Doris ,  Meikei Ieong ,  Devendra K. Sadana

    发明人： Diane C. Boyd ,  Bruce B. Doris ,  Meikei Ieong ,  Devendra K. Sadana

    IPC分类号： H01L21/302

    CPC分类号： H01L21/28194 ,  H01L21/26533 ,  H01L21/28202 ,  H01L29/1083 ,  H01L29/49 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78

    摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.

    摘要翻译： 本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。 具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。 提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。

    Self-aligned planar double-gate process by amorphization
    35.
    发明授权
    Self-aligned planar double-gate process by amorphization 有权
    通过非晶化自对准平面双栅极工艺

    公开(公告)号：US06833569B2

    公开(公告)日：2004-12-21

    申请号：US10328234

    申请日：2002-12-23

    申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin C. Jones

    发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Suryanarayan G. Hegde ,  Meikei Ieong ,  Erin C. Jones

    IPC分类号： H01L27148

    CPC分类号： H01L29/66916 ,  H01L29/42316 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/802

    摘要： The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.

    摘要翻译： 本发明提供一种用于制造具有与前门对准的背栅的平面DGFET的方法。 本发明的方法通过在后门的一部分中产生载流子耗尽区来实现该对准。 载流子耗尽区减小了源极/漏极区域和后栅极之间的电容，从而提供了高性能自对准平面双栅极场效应晶体管（DGFET）。 本发明还提供一种具有与前门对准的后门的平面DGFET。 通过在后门的部分中提供载流子耗尽区来实现前到后栅极对准。

    Hybrid planar and FinFET CMOS devices
    36.
    发明授权
    Hybrid planar and FinFET CMOS devices 有权
    混合平面和FinFET CMOS器件

    公开(公告)号：US07250658B2

    公开(公告)日：2007-07-31

    申请号：US11122193

    申请日：2005-05-04

    申请人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    发明人： Bruce B. Doris ,  Diane C. Boyd ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub T. Kedzierski ,  Min Yang

    IPC分类号： H01L29/772

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

    摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。