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47 条记录 (耗时 0.033 秒)

    Structure and method for fabricating integrated circuits
    31.
    发明授权
    Structure and method for fabricating integrated circuits 失效
    集成电路制造的结构和方法

    公开(公告)号：US5500557A

    公开(公告)日：1996-03-19

    申请号：US126673

    申请日：1993-09-24

    申请人： Tsiu C. Chan ,  Frank R. Bryant ,  Lun-Tseng Lu ,  Che-Chia Wei

    发明人： Tsiu C. Chan ,  Frank R. Bryant ,  Lun-Tseng Lu ,  Che-Chia Wei

    IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L23/48

    CPC分类号： H01L23/5283 ,  H01L23/53271 ,  H01L2924/0002

    摘要： A structure and method for fabricating integrated circuits which provides for the detection of residual conductive material. A first conductive layer is deposited over the integrated circuit and patterned to define a first interconnect layer. An insulating layer is then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during patterning of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.

    摘要翻译： 用于制造集成电路的结构和方法，其提供残留导电材料的检测。 第一导电层沉积在集成电路上并被图案化以限定第一互连层。 然后在集成电路上形成绝缘层。 然后沉积和图案化第二导电层以限定第二互连层。 当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在图案化第二互连层期间形成剩余的导电材料。 为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

    Interconnect structure for an integrated circuit
    32.
    发明授权
    Interconnect structure for an integrated circuit 失效
    集成电路的互连结构

    公开(公告)号：US5313084A

    公开(公告)日：1994-05-17

    申请号：US891450

    申请日：1992-05-29

    申请人： Che-Chia Wei

    发明人： Che-Chia Wei

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L29/540

    CPC分类号： H01L21/76889 ,  H01L21/76895

    摘要： A local interconnect structure for an integrated circuit is formed from a patterned refractory metal silicide. The local interconnect has an overlying oxide layer, which prevents part of the amorphous silicon used to form the interconnect from becoming silicided. This results in a local interconnect layer which has thinner silicide portions than silicide regions formed over adjacent source/drain regions and gate electrodes.

    摘要翻译： 用于集成电路的局部互连结构由图案化的难熔金属硅化物形成。 局部互连具有覆盖的氧化物层，其防止用于形成互连的非晶硅的一部分变成硅化物。 这导致局部互连层，其具有比在相邻源极/漏极区域和栅电极上形成的硅化物区更薄的硅化物部分。

    Method of forming a gate overlap LDD structure
    33.
    发明授权
    Method of forming a gate overlap LDD structure 失效
    形成栅极重叠LDD结构的方法

    公开(公告)号：US5304504A

    公开(公告)日：1994-04-19

    申请号：US71563

    申请日：1993-06-02

    申请人： Che-Chia Wei ,  Ravishankar Sundaresan

    发明人： Che-Chia Wei ,  Ravishankar Sundaresan

    IPC分类号： B01D61/02 ,  B01D61/08 ,  B01D61/12 ,  H01L21/265

    CPC分类号： B01D61/025 ,  B01D61/08 ,  B01D61/12

    摘要： A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

    摘要翻译： 提供一种用于形成集成电路的栅极重叠LDD结构的方法，以及根据该集成电路形成的集成电路。 在衬底上形成氧化物层。 四层栅电极形成为反T形。 在下面的氧化物层上形成第一多晶硅层。 在第一多晶硅层上形成第一导电层。 在第一导电层上形成第二多晶硅层。 然后在第二多晶硅层上形成第二导电层。 蚀刻第二导电和多晶硅层以暴露下面的第一导电层的一部分。 在与第二导电层和多晶硅层相邻的衬底中形成轻掺杂漏极区。 侧壁氧化物间隔物形成在第二导电层和多晶硅层的侧面上，并且在第一导电层的顶部上。 第一导电和多晶硅层被蚀刻暴露一部分下面的氧化物层。 源极/漏极区域形成在与第一导电层和多晶硅层相邻的衬底中。

    Gate overlapping LDD structure
    34.
    发明授权
    Gate overlapping LDD structure 失效
    门重叠LDD结构

    公开(公告)号：US5276347A

    公开(公告)日：1994-01-04

    申请号：US809398

    申请日：1991-12-18

    申请人： Che-Chia Wei ,  Ravishankar Sundaresan

    发明人： Che-Chia Wei ,  Ravishankar Sundaresan

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/7836

    摘要： A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

    摘要翻译： 提供一种用于形成集成电路的栅极重叠LDD结构的方法，以及根据该集成电路形成的集成电路。 在衬底上形成氧化物层。 四层栅电极形成为反T形。 在下面的氧化物层上形成第一多晶硅层。 在第一多晶硅层上形成第一导电层。 在第一导电层上形成第二多晶硅层。 然后在第二多晶硅层上形成第二导电层。 蚀刻第二导电和多晶硅层以暴露下面的第一导电层的一部分。 在与第二导电层和多晶硅层相邻的衬底中形成轻掺杂漏极区。 侧壁氧化物间隔物形成在第二导电层和多晶硅层的侧面上，并且在第一导电层的顶部上。 第一导电和多晶硅层被蚀刻暴露一部分下面的氧化物层。 源极/漏极区域形成在与第一导电层和多晶硅层相邻的衬底中。

    Method of making oxide-isolated source/drain transistor
    36.
    发明授权
    Method of making oxide-isolated source/drain transistor 失效
    制造氧化物隔离源/漏晶体管的方法

    公开(公告)号：US4963502A

    公开(公告)日：1990-10-16

    申请号：US416566

    申请日：1989-10-03

    申请人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

    发明人： Clarence W. Teng ,  Thomas E. Tang ,  Che-Chia Wei

    IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

    CPC分类号： H01L29/66636 ,  H01L21/28525 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0847 ,  H01L27/0921 ,  H01L27/0928

    摘要： A MOS bulk device having source/drain-contact regions 36 which are almost completely isolated by a dielectric 35. These "source/drain" regions 36 are formed by using a silicon etch to form a recess, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes contact between the oxide-isolated source/drain-contact regions 36 and the channel region 33 of the active device. Outdiffusion through the small area of this contact will form small diffusions 44 in silicon, which act as the electrically effective source/drain regions. Use of sidewall nitride filaments 30 on the gate permits the silicon etch step to be self-aligned.

    摘要翻译： 具有源极/漏极 - 接触区域36的MOS体器件，其几乎完全由电介质35隔离。这些“源极/漏极”区域36通过使用硅蚀刻形成凹部，用氧化物衬在蚀刻的凹槽上，以及 回填多晶硅。 短的各向同性氧化物蚀刻，随后是多晶硅长丝沉积，然后在氧化物隔离的源极/漏极 - 接触区域36和有源器件的沟道区域33之间接触。 通过该接触的小面积的扩散将在硅中形成小的扩散部分44，其作为电有效的源极/漏极区域。 在栅极上使用侧壁氮化物细丝30允许硅蚀刻步骤自对准。

    Method of forming an integrated circuit device
    39.
    发明授权
    Method of forming an integrated circuit device 失效
    形成集成电路器件的方法

    公开(公告)号：US6027979A

    公开(公告)日：2000-02-22

    申请号：US73417

    申请日：1998-05-06

    申请人： Che-Chia Wei

    发明人： Che-Chia Wei

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L29/66492 ,  H01L21/823814 ,  H01L29/6659

    摘要： A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

    摘要翻译： 掩模用于集成电路器件中的轻掺杂漏极和光晕注入。 掩模只露出与场效应晶体管栅电极相邻的衬底的部分。 由于光晕植入仅在晶体管通道附近进行，在其中它执行有用的功能，因此获得了足够的器件可靠性和性能。 由于从不需要的有源区的那些部分掩盖光晕注入，所以有源区域结电容降低。 这种降低的电容导致提高的晶体管切换速度。 用于限定轻掺杂的漏极和晕圈注入区域的掩模可以容易地由已经存在的栅极和有源区域几何形状的直接组合形成。