公开(公告)号：US20050095945A1

公开(公告)日：2005-05-05

申请号：US10695810

申请日：2003-10-30

Applicant: Jung-Fang Chang ,  Chich-Shang Chang ,  Chi-Lin Chen

Inventor： Jung-Fang Chang ,  Chich-Shang Chang ,  Chi-Lin Chen

IPC: B32B37/16 ,  G02F1/1333 ,  G09F9/30 ,  H01J9/24 ,  H01J9/00

CPC classification number: G02F1/133305

Abstract: A method for manufacturing a flexible panel is disclosed, which has the following steps. First, a first substrate having a plurality of functional switches or conducting lines thereon is provided. Then, a second substrate is bonded on the functional switches or conducting lines, and the first substrate is thinned to a predetermined thickness subsequently. Afterwards, a flexible third substrate is adhered on the first substrate, wherein the first substrate is sandwiched between the second substrate and the third substrate. Finally, the second substrate is removed.

Abstract translation: 公开了一种制造柔性面板的方法，其具有以下步骤。 首先，提供具有多个功能开关或导线的第一基板。 然后，第二基板被接合在功能开关或导线上，并且第一基板随后变薄到预定厚度。 之后，将柔性第三基板粘附在第一基板上，其中第一基板夹在第二基板和第三基板之间。 最后，去除第二衬底。

公开(公告)号：US06181123B2

公开(公告)日：2001-01-30

申请号：US09267879

申请日：1999-03-11

Applicant: Shyh-Jye Jou ,  Chi-Lin Chen ,  Li-Kuo Liu

Inventor： Shyh-Jye Jou ,  Chi-Lin Chen ,  Li-Kuo Liu

IPC: G05B2402

CPC classification number: H02M3/157

Abstract: A digital programmable DC—DC voltage-down converter which can be used in a low voltage and low power digital circuit design is disclosed. The DC—DC voltage-down converter includes at least a digitally controlled oscillator (DCO), a pulse-width modulator (PWM), a gate driver, and a switching-type voltage-down converter. Duty cycle and operating frequency of the modulated signal are controlled by using two digital control signals. Furthermore, combining the pulse-width modulator and the digitally controlled oscillator (DCO), the duty cycle of the generated clock is more robustly stable for different frequencies during process variation.

Abstract translation: 公开了可用于低电压和低功率数字电路设计的数字可编程DC-DC降压转换器。 DC-DC降压转换器至少包括数字控制振荡器（DCO），脉冲宽度调制器（PWM），栅极驱动器和开关型降压转换器。 通过使用两个数字控制信号来控制调制信号的占空比和工作频率。 此外，组合脉冲宽度调制器和数字控制振荡器（DCO）时，生成的时钟的占空比在过程变化期间对于不同的频率更稳健。

公开(公告)号：US07960731B2

公开(公告)日：2011-06-14

申请号：US11870426

申请日：2007-10-11

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen ,  Chi-Ming Chang

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen ,  Chi-Ming Chang

IPC: H01L21/84

CPC classification number: H01L27/1288 ,  G02F1/1368 ,  H01L27/124

Abstract: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.

Abstract translation: 提供多层互补导电线结构，其制造方法和TFT（薄膜晶体管）显示阵列的制造方法。 具有多层互补导电线结构的TFT的工艺与当前工艺相比不需要增加掩模数，并且能够解决显示器内部的线的电阻问题。

公开(公告)号：US07560365B2

公开(公告)日：2009-07-14

申请号：US11226679

申请日：2005-09-14

Applicant: Jia-Xing Lin ,  Chi-Lin Chen

Inventor： Jia-Xing Lin ,  Chi-Lin Chen

IPC: H01L21/36 ,  H01L21/20

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/78645

Abstract: A method for fabricating a semiconductor device includes providing a substrate, forming an amorphous silicon layer over the substrate, forming a heat retaining layer on the amorphous silicon layer, patterning the heat retaining layer, and irradiating the patterned heat retaining layer.

Abstract translation: 一种制造半导体器件的方法包括提供衬底，在衬底上形成非晶硅层，在非晶硅层上形成保温层，图案化保温层，并照射图案化保温层。

公开(公告)号：US07435667B2

公开(公告)日：2008-10-14

申请号：US10772511

申请日：2004-02-05

Applicant: Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Yih-Rong Luo

Inventor： Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Yih-Rong Luo

IPC: H01L21/20

CPC classification number: H01L21/02686 ,  C30B13/24 ,  C30B29/06 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78603

Abstract: A heat sink layer is formed on portions of a substrate, and then an amorphous silicon layer is formed thereon. The heat coefficient of the sink layer is greater than that of the substrate. When an excimer laser heats the amorphous silicon layer to crystallize the amorphous silicon, nucleation sites are formed in the amorphous silicon layer on the heat sink layer. Next, laterally expanding crystallization occurs in the amorphous silicon layer on the substrate to form polysilicon having a crystal size of a micrometer.

Abstract translation: 在衬底的部分上形成散热层，然后在其上形成非晶硅层。 吸收层的热系数大于衬底的热系数。 当准分子激光器加热非晶硅层以使非晶硅结晶时，在散热层上的非晶硅层中形成成核位点。 接着，在基板上的非晶硅层发生横向膨胀结晶，形成晶体尺寸为微米的多晶硅。

公开(公告)号：US20080108195A1

公开(公告)日：2008-05-08

申请号：US11963854

申请日：2007-12-24

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L21/336

CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

公开(公告)号：US07339190B2

公开(公告)日：2008-03-04

申请号：US11308710

申请日：2006-04-25

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L29/76

CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

公开(公告)号：US20070105373A1

公开(公告)日：2007-05-10

申请号：US11270862

申请日：2005-11-09

Applicant: Liang-Tang Wang ,  Chi-Lin Chen ,  I-Hsuan Peng ,  Jung-Fang Chang ,  Chin-Jen Huang

Inventor： Liang-Tang Wang ,  Chi-Lin Chen ,  I-Hsuan Peng ,  Jung-Fang Chang ,  Chin-Jen Huang

IPC: H01L21/44

CPC classification number: H01L21/02532 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/5096 ,  H01L21/02422 ,  H01L21/0262 ,  H01L27/1214

Abstract: A method for forming a polysilicon film in a plasma-assisted chemical vapor deposition (CVD) system including a chamber in which a first electrode and a second electrode spaced apart from the first electrode are provided comprises providing a substrate on the second electrode, the substrate including a surface exposed to the first electrode, applying a first power to the first electrode for generating a plasma in the chamber, applying a second power to the second electrode during a nucleation stage of the polysilicon film for ion bombarding the surface of the substrate, and flowing an erosive gas into the chamber.

Abstract translation: 一种在等离子体辅助化学气相沉积（CVD）系统中形成多晶硅膜的方法，包括：设置有与第一电极间隔开的第一电极和第二电极的腔室，包括在第二电极上设置衬底， 包括暴露于第一电极的表面，向第一电极施加第一功率以在腔室中产生等离子体，在用于离子轰击衬底表面的多晶硅膜的成核阶段期间向第二电极施加第二功率， 并将侵蚀性气体流入室内。

公开(公告)号：US20070085115A1

公开(公告)日：2007-04-19

申请号：US11308612

申请日：2006-04-12

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Chi-Wen Chen ,  Ting-Chang Chang

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Chi-Wen Chen ,  Ting-Chang Chang

IPC: H01L31/113 ,  H01L31/062 ,  H01L21/84 ,  H01L21/00

CPC classification number: H01L27/1214 ,  H01L29/40117 ,  H01L29/66833

Abstract: A memory cell, suitable for being disposed on a substrate, comprises a poly-Si island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-Si island is disposed on the substrate and includes a source doped region, a drain doped region and a channel region there-between. The first dielectric layer is disposed on the poly-Si island, the trapping layer is disposed on the first dielectric layer, the second dielectric layer is disposed on the trapping layer and the control gate is disposed on the second dielectric layer. The above-described memory cell can be integrated into the manufacturing process of a low temperature polysilicon LCD panel (LTPS LCD panel) or an organic light emitting display panel (OLED panel).

Abstract translation: 适用于设置在基板上的存储单元包括多晶硅岛，第一介电层，俘获层，第二介电层和控制栅。 多晶硅岛设置在衬底上，包括源极掺杂区，漏极掺杂区和其间的沟道区。 第一介电层设置在多晶硅岛上，俘获层设置在第一介电层上，第二介电层设置在俘获层上，控制栅设置在第二介质层上。 上述存储单元可以集成到低温多晶硅LCD面板（LTPS LCD面板）或有机发光显示面板（OLED面板）的制造过程中。

公开(公告)号：US07161226B2

公开(公告)日：2007-01-09

申请号：US11131084

申请日：2005-05-17

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

IPC: H01L29/00

CPC classification number: H01L23/5221 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered wire structure includes a substrate, a plurality of first conductive lines formed in a first layer over the substrate extending in parallel to each other in a first direction, a plurality of second conductive lines formed in a second layer over the first layer extending in parallel to each other in a second direction orthogonal to the first direction, a plurality of sets of third conductive lines formed in the second layer extending in the first direction, each set of third conductive lines corresponding to one of the first conductive lines, and a plurality of sets of conductive paths formed between the first layer and the second layer, each set of conductive paths corresponding to one of the first conductive lines and one set of third conductive lines and electrically connecting the corresponding first conductive line to the corresponding set of third conductive lines.

Abstract translation: 一种多层导线结构，包括：基板，形成在第一层上的多个第一导电线，该第一导电线在基板上沿着第一方向彼此平行地延伸;多个第二导电线，形成在第一层上的第一层 在与第一方向正交的第二方向上彼此平行地延伸的多个第三导线组，所述第二导电线形成在第一方向上延伸，每组第三导线对应于第一导线之一， 以及形成在所述第一层和所述第二层之间的多组导电路径，每组导电路径对应于所述第一导电线中的一条和一组第三导电线，并将相应的第一导电线电连接到相应的集合 的第三导线。