公开(公告)号：US08572333B2

公开(公告)日：2013-10-29

申请号：US12532828

申请日：2008-12-30

申请人： Emanuele Confalonieri ,  Daniele Vimercati

发明人： Emanuele Confalonieri ,  Daniele Vimercati

IPC分类号： G06F13/00

CPC分类号： G11C13/0004 ,  G11C7/04 ,  G11C13/0033 ,  G11C16/3431

摘要： A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when the temperature exceeds a threshold temperature for an amount of time.

摘要翻译： 描述了一种用于测量非易失性存储器中的温度并且当温度超过阈值温度一段时间时刷新非易失性存储器的至少一部分的方法和装置。

公开(公告)号：US20120314522A1

公开(公告)日：2012-12-13

申请号：US13519846

申请日：2009-12-30

申请人： Daniele Balluchi ,  Daniele Vimercati ,  Graziano Mirichigni

发明人： Daniele Balluchi ,  Daniele Vimercati ,  Graziano Mirichigni

IPC分类号： G11C5/14 ,  H03K3/00

CPC分类号： H03K3/012 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4072

摘要： An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles Of the clock signal, the buffer is automatically powered up.

摘要翻译： 集成电路可以具有耦合到缓冲器（24）的时钟输入引脚。 缓冲器可以向诸如存储器的集成电路芯片提供时钟信号（28）。 为了节省电力，缓冲区掉电。 当准备使用时，缓冲区被快速备份。 在一个实施例中，响应于预定数量的时钟信号切换，缓冲器被自动加电。

公开(公告)号：US07646644B2

公开(公告)日：2010-01-12

申请号：US11460531

申请日：2006-07-27

申请人： Efrem Bolandrina ,  Daniele Vimercati ,  Corrado Villa

发明人： Efrem Bolandrina ,  Daniele Vimercati ,  Corrado Villa

IPC分类号： G11C16/26 ,  G11C7/14

CPC分类号： G11C11/5642 ,  G11C16/28 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A memory device includes a group of memory cells organized in rows and columns and a first addressing circuit for addressing said memory cells of said group on the basis of a cell address. The device further includes a plurality of sets of reference cells, associated to the group, each of said set having a plurality of reference cells, and a second addressing circuit for addressing one of the reference cells during operations of read and verify of addressed memory cells.

摘要翻译： 存储器件包括以行和列组织的一组存储器单元和用于基于单元地址对所述组的所述存储器单元寻址的第一寻址电路。 所述设备还包括与所述组相关联的多组参考单元，所述组中的每一个具有多个参考单元，以及用于在读取和验证寻址的存储器单元的操作期间寻址所述参考单元之一的第二寻址电路 。

公开(公告)号：US20070279980A1

公开(公告)日：2007-12-06

申请号：US11753368

申请日：2007-05-24

申请人： Stefan Schippers ,  Daniele Vimercati ,  Efrem Bolandrina

发明人： Stefan Schippers ,  Daniele Vimercati ,  Efrem Bolandrina

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C11/5642

摘要： The invention relates to a reading method of a non-volatile electronic device of the multilevel type, the device comprises at least one first and one second memory bank each of said memory banks comprises a plurality of transistor cells organized in a matrix with a plurality of rows or wordlines and a plurality of columns or bitlines, at least one of said transistor cells being a reference cell containing a reference value, said bitlines being connected to at least one group of sense amplifiers, which comprises in turn a reference terminal and at least one signal output.A crossed electric connection is provided between the reference terminal of at least one group of sense amplifiers of the first memory bank to an output of a subgroup of sense amplifiers of the second memory bank, and vice versa, and the subgroup of sense amplifiers associated with a memory bank is used as a connection to said reference cell during the reading step of the other memory bank.

摘要翻译： 本发明涉及一种多电平型非易失性电子装置的读取方法，该装置包括至少一个第一和第二存储体，每个存储体包括多个晶体管单元，其以矩阵形式组织成多个， 行或字线以及多个列或位线，所述晶体管单元中的至少一个是包含参考值的参考单元，所述位线连接至至少一组读出放大器，所述至少一组读出放大器依次包括参考端，并且至少包括参考端 一个信号输出。 在第一存储器组的至少一组读出放大器的参考端子与第二存储器组的读出放大器的子组的输出之间提供交叉电连接，反之亦然，以及与第 在另一个存储体的读取步骤期间，存储体被用作与所述参考单元的连接。

公开(公告)号：US20050040977A1

公开(公告)日：2005-02-24

申请号：US10861340

申请日：2004-06-04

申请人： Stefan Schippers ,  Daniele Vimercati ,  Efrem Bolandrina

发明人： Stefan Schippers ,  Daniele Vimercati ,  Efrem Bolandrina

IPC分类号： G11C7/14 ,  G11C16/28 ,  H03M1/10

CPC分类号： G11C16/28 ,  G11C7/14

摘要： A method is described for generating a reference current for sense amplifiers connected to cells of a memory matrix comprising the steps of generating a first reference current analog signal through a reference cell, performing an analog-to-digital conversion of the first analog signal into a reference current digital signal, sending the digital signal on a connection line to the sense amplifiers, and performing a digital-to-analog conversion of the digital signal into a second reference current analog signal to be applied as reference current to the sense amplifiers.

摘要翻译： 描述了一种用于产生连接到存储器矩阵的单元的读出放大器的参考电流的方法，包括以下步骤：通过参考单元产生第一参考电流模拟信号，执行第一模拟信号的模数转换为 参考电流数字信号，将连接线上的数字信号发送到感测放大器，并且将数字信号进行数模转换成第二参考电流模拟信号，以作为参考电流施加到感测放大器。

公开(公告)号：US20050013170A1

公开(公告)日：2005-01-20

申请号：US10835538

申请日：2004-04-29

申请人： Daniele Vimercati ,  Stefan Schippers ,  Graziano Mirichigni ,  Corrado Villa

发明人： Daniele Vimercati ,  Stefan Schippers ,  Graziano Mirichigni ,  Corrado Villa

IPC分类号： G11C8/08 ,  G11C16/08 ,  G11C11/34

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

摘要翻译： 提出了一种用于驱动控制非易失性存储器件的至少一个存储器单元的存储器线路的电路，该电路响应于第一和第二选择信号，每个选择信号适合于采用第一逻辑值或第二逻辑值 ，其中所述电路包括用于将所述第一选择信号转换为第一操作信号的第一电平移位器和用于将所述第二选择信号转换为第二操作信号的第二电平移位器，每个电平移位器包括用于移动所述逻辑中的一个的第一移位装置 将相应的选择信号的值转换为第一偏置电压;以及选择器，用于根据第二操作信号将第一操作信号或第二偏置电压施加到存储器线; 在本发明的电路中，每个电平移位器还包括第二移位装置，用于将相应的选择信号的另一个逻辑值移位到第二偏置电压。

公开(公告)号：US08730754B2

公开(公告)日：2014-05-20

申请号：US13085454

申请日：2011-04-12

申请人： Gerald Barkley ,  Efrem Bolandrina ,  Daniele Vimercati

发明人： Gerald Barkley ,  Efrem Bolandrina ,  Daniele Vimercati

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C8/14

摘要： A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.

摘要翻译： 存储器件包括在相邻存储器块之间共享组件的字线解码器电路。 字线解码器电路包括多个电平，其中至少一个电平被分离，驱动一个相邻存储器块中的一半字线并驱动另一相邻存储器块中的一半字线。 存储器块具有耦合到一个相邻解码器电路的每隔一个字线，并且剩余字线耦合到另一相邻解码器电路。

公开(公告)号：US20140098608A1

公开(公告)日：2014-04-10

申请号：US13384999

申请日：2011-06-10

申请人： Gerald John Barkley ,  Daniele Vimercati ,  Pierguido Garofalo

发明人： Gerald John Barkley ,  Daniele Vimercati ,  Pierguido Garofalo

IPC分类号： G11C16/10 ,  G11C16/26

CPC分类号： G11C5/025 ,  G11C7/1042 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

摘要： Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.

摘要翻译： 本文公开的主题涉及方法和装置，诸如包括这种存储装置的存储装置和系统。 在一个装置示例中，可以采用多个块配置。 块配置可以包括类似掺杂的半导体开关的布置。 块配置可以选择存储器阵列的相应瓦片，相应瓦片的特定存储器单元，并且选择应用于特定存储器单元的存储器操作。 存储器阵列的特定切片内的紧邻相邻的块配置可以基本上镜像，并且在存储器阵列的分离的紧邻相邻切片中的紧密相邻的块配置可以基本相似。 用于基本上镜像的块配置的类似掺杂的半导体开关的类似的掺杂扩散区可以被布置成电共享公共的电位信号值电平。 还公开了其它装置和方法。

公开(公告)号：US20120287740A1

公开(公告)日：2012-11-15

申请号：US13106359

申请日：2011-05-12

申请人： Daniele Vimercati

发明人： Daniele Vimercati

IPC分类号： G11C7/12 ,  H03F3/45

CPC分类号： G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  H03F3/45762 ,  H03F2200/261 ,  H03F2203/45536 ,  H03F2203/45544 ,  H03F2203/45551

摘要： Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances.

摘要翻译： 公开了用于感测存储器单元的数据状态的感测放大器，存储器以及装置和方法。 示例性装置包括：差分放大器，被配置为放大施加到第一和第二放大器输入节点的电压之间的电压差以提供输出。 该示例设备还包括耦合到第一和第二放大器输入节点的第一和第二电容。 耦合到第一和第二电容的开关块被配置为在参考输入节点的第一阶段期间将第一和第二电容耦合到第一放大器输入节点。 开关块还被配置为在第一阶段期间将放大器的输出耦合到第二放大器输入节点以建立补偿条件。 在第二阶段期间，开关块将其输入节点耦合到第一和第二电容。

公开(公告)号：US20120124317A1

公开(公告)日：2012-05-17

申请号：US12947781

申请日：2010-11-16

申请人： Graziano Mirichigni ,  Daniele Vimercati

发明人： Graziano Mirichigni ,  Daniele Vimercati

IPC分类号： G06F12/00

CPC分类号： G06F13/24 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0253 ,  G06F2212/702 ,  G11C5/066 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/2209 ,  G11C2216/22

摘要： Subject matter disclosed herein relates to read and write processes of a memory device.

摘要翻译： 本文公开的主题涉及存储器件的读取和写入过程。