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公开(公告)号：US20110302353A1
公开(公告)日：2011-12-08
申请号：US12532828
申请日：2008-12-30
IPC分类号： G06F12/02
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0033 , G11C16/3431
摘要： A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when the temperature exceeds a threshold temperature for an amount of time.
摘要翻译： 描述了一种用于测量非易失性存储器中的温度并且当温度超过阈值温度一段时间时刷新非易失性存储器的至少一部分的方法和装置。
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公开(公告)号：US08572333B2
公开(公告)日：2013-10-29
申请号：US12532828
申请日：2008-12-30
IPC分类号： G06F13/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0033 , G11C16/3431
摘要： A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when the temperature exceeds a threshold temperature for an amount of time.
摘要翻译： 描述了一种用于测量非易失性存储器中的温度并且当温度超过阈值温度一段时间时刷新非易失性存储器的至少一部分的方法和装置。
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公开(公告)号：US20120263005A1
公开(公告)日：2012-10-18
申请号：US13085454
申请日：2011-04-12
IPC分类号： G11C8/10
摘要： A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.
摘要翻译： 存储器件包括在相邻存储器块之间共享组件的字线解码器电路。 字线解码器电路包括多个电平，其中至少一个电平被分离，驱动一个相邻存储器块中的一半字线并驱动另一相邻存储器块中的一半字线。 存储器块具有耦合到一个相邻解码器电路的每隔一个字线，并且剩余字线耦合到另一相邻解码器电路。
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公开(公告)号：US08243497B1
公开(公告)日：2012-08-14
申请号：US12628153
申请日：2009-11-30
申请人： Fabio Pellizzer , Agostino Pirovano , Augusto Benvenuti , Daniele Vimercati , Andrea Redaelli , Gerald Barkley
发明人： Fabio Pellizzer , Agostino Pirovano , Augusto Benvenuti , Daniele Vimercati , Andrea Redaelli , Gerald Barkley
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0033 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2013/008 , G11C2213/79
摘要： A Phase Change Memory device with reduced programming disturbance and its operation are described. The Phase Change Memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.
摘要翻译： 描述了具有减少的编程干扰及其操作的相变存储器件。 相变存储器包括具有字线和位线的阵列，以及耦合到与寻址位线相邻的位线的电压控制元件，以将相邻位线的电压维持在允许的范围内。
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公开(公告)号：US08184487B2
公开(公告)日：2012-05-22
申请号：US12871755
申请日：2010-08-30
IPC分类号： G11C7/10
摘要： A method may comprise executing a read operation to access a memory array by performing a preactive command to include a row-address-write operation and a bitline precharge and column selection operation and performing an activate command including a column-address-write operation and a row-decode-selection operation.
摘要翻译： 方法可以包括通过执行包括行地址写入操作和位线预充电和列选择操作的预激活命令来执行访问存储器阵列的读操作，并执行包括列地址写操作和 行解码选择操作。
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公开(公告)号：US07321512B2
公开(公告)日：2008-01-22
申请号：US11381426
申请日：2006-05-03
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C8/14 , G11C11/5642 , G11C16/08 , G11C16/30
摘要： A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp. A respective local ramp generating circuit is provided for each array sector and for the array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.
摘要翻译： 非易失性存储器件包括被组织成多个阵列扇区的存储器单元的阵列，每个阵列扇区通过阵列字线被单独寻址。 参考单元阵列可通过参考字线寻址。 为每个阵列扇区提供相应的电压斜坡发生器，用于在阵列字线上产生用于读取其中的存储单元的电压斜坡，并且为每个参考单元阵列提供参考单元阵列，用于在其上的参考单元的基准字线上产生电压斜坡 。 相应的行解码电路耦合在每个相应的电压斜坡发生器和对应的参考字线或阵列字线之间。 电流发生器产生要注入到选定的阵列扇区中的电路节点上的参考电池阵列的电路节点上的电流，以在电路节点上产生类似于所产生的电压斜坡的电压斜坡。 为每个阵列扇区和参考单元阵列提供相应的本地斜坡发生电路，并且将基于对应的寻址阵列字线或参考字线的电路节点的电荷的充电电流传送到相应的行解码器 字线
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公开(公告)号：US07272059B2
公开(公告)日：2007-09-18
申请号：US10913128
申请日：2004-08-06
IPC分类号： G11C7/00
摘要： A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential. At least the precharge circuit includes a precharge negative feedback control loop, for controlling the memory bit line potential during the precharge phase. A same circuit element is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.
摘要翻译： 一种用于半导体存储器的感测电路，包括一个电路分支，用于电耦合到已连接到要感测的存储器单元的存储器位线。 提供位线预充电电路，用于在存储器单元感测操作的预充电阶段将存储器位线预充电到预定电位。 评估电路与用于评估存储器单元感测操作的评估阶段期间在存储器位线上产生的电量的存储器位线相关联; 在存储位线上产生的电量表示存储单元的信息内容。 位线预充电电路适于对存储器位线进行充电和放电，使得在预充电阶段开始时的存储位线初始电位无论达到预定的位线电位。 位线预充电电路适于根据存储器位线电位和预定位线电位之间的差异来对存储器位线进行充电和放电。 至少预充电电路包括预充电负反馈控制回路，用于在预充电阶段期间控制存储器位线电位。 提供了相同的电路元件，其在预充电阶段期间控制存储器位线电位，并且在存储器单元感测操作的评估阶段期间评估电量。
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公开(公告)号：US20060209594A1
公开(公告)日：2006-09-21
申请号：US11367707
申请日：2006-03-02
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/32 , G11C2211/5634
摘要： A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, sense amplifiers that detect the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, a logic unit that determines a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, and a time shift structure that time shifts at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.
摘要翻译： 存储器件包括多个存储器单元和比较电路，其将所选择的存储器单元组与至少一个具有阈值电压的参考单元进行比较。 比较电路包括偏置电路，该偏置电路将具有基本上单调的时间图案的偏置电压施加到所选择的存储器单元和至少一个参考单元，检测放大器，其通过每个选择的存储器的单元电流检测比较电流的到达 单元和每个参考单元的参考电流;逻辑单元，其根据比较电流到达相应的单元电流和至少一个参考电流的时间关系来确定每个选择的存储单元的状态;以及 时移结构，其根据至少一个预定间隔时间移动至少一个所述检测，以模拟与具有另一阈值电压的至少一个另外的参考小区的比较。
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公开(公告)号：US07023738B2
公开(公告)日：2006-04-04
申请号：US10835538
申请日：2004-04-29
IPC分类号： G11C16/06
摘要： A circuit is proposed for driving a memory line controlling at least one memory cell of a non-volatile memory device, the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter for converting the first selection signal into a first operative signal and a second level shifter for converting the second selection signal into a second operative signal, each level shifter including first shifting means for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means for shifting another of the logic values of the corresponding selection signal to the second bias voltage.
摘要翻译： 提出了一种用于驱动控制非易失性存储器件的至少一个存储器单元的存储器线路的电路，该电路响应于第一和第二选择信号，每个选择信号适合于采用第一逻辑值或第二逻辑值 ，其中所述电路包括用于将所述第一选择信号转换为第一操作信号的第一电平移位器和用于将所述第二选择信号转换为第二操作信号的第二电平移位器，每个电平移位器包括用于移动所述逻辑中的一个的第一移位装置 将相应的选择信号的值转换为第一偏置电压;以及选择器，用于根据第二操作信号将第一操作信号或第二偏置电压施加到存储器线; 在本发明的电路中，每个电平移位器还包括第二移位装置，用于将相应的选择信号的另一个逻辑值移位到第二偏置电压。
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公开(公告)号：US08824235B2
公开(公告)日：2014-09-02
申请号：US13519846
申请日：2009-12-30
IPC分类号： G11C5/14
CPC分类号： H03K3/012 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4072
摘要： An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles of the clock signal, the buffer is automatically powered up.
摘要翻译： 集成电路可以具有耦合到缓冲器（24）的时钟输入引脚。 缓冲器可以向诸如存储器的集成电路芯片提供时钟信号（28）。 为了节省电力，缓冲区掉电。 当准备使用时，缓冲区被快速备份。 在一个实施例中，响应于预定数量的时钟信号的切换，缓冲器自动上电。
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