利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

83 条记录 (耗时 0.033 秒)

    Semiconductor component with silicon wiring and method of fabricating the component
    31.
    发明授权
    Semiconductor component with silicon wiring and method of fabricating the component 有权
    具有硅布线的半导体元件及其制造方法

    公开(公告)号：US06429520B1

    公开(公告)日：2002-08-06

    申请号：US09391039

    申请日：1999-09-07

    申请人： Ronald Kakoschke ,  Regina Stokan

    发明人： Ronald Kakoschke ,  Regina Stokan

    IPC分类号： H01L2348

    CPC分类号： H01L21/28568 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor component has local silicon wiring. A first silicon region and a second silicon region are doped with dopants of opposite conductivity. The second silicon region is arranged at least partially over the first silicon region and is separated from it by an insulation layer. The insulation layer is formed with an opening. A conductive layer is disposed at the opening. The conductive layer is composed of a metal, a metal nitride or a combination thereof and connects the first and the second silicon regions electrically to one another.

    摘要翻译： 半导体元件具有局部硅布线。 第一硅区域和第二硅区域掺杂有相反导电性的掺杂剂。 第二硅区域至少部分地布置在第一硅区域之上并且通过绝缘层与其分离。 绝缘层形成有开口。 导电层设置在开口处。 导电层由金属，金属氮化物或其组合构成，并且将第一和第二硅区彼此电连接。

    Method for producing an integrated field-effect transistor
    32.
    发明授权
    Method for producing an integrated field-effect transistor 有权
    用于制造集成场效应晶体管的方法

    公开(公告)号：US08518759B2

    公开(公告)日：2013-08-27

    申请号：US12848576

    申请日：2010-08-02

    申请人： Ronald Kakoschke

    发明人： Ronald Kakoschke

    IPC分类号： H01L21/00

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7855 ,  H01L29/78612

    摘要： A method for fabricating a field-effect transistor is provided. The method includes forming a substrate region, forming two terminal regions at the substrate region, one terminal region being a source region and the other terminal region being a drain region, forming two electrically insulating insulating layers, which are arranged at mutually opposite sides of the substrate region and are adjoined by control regions, forming an electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region the conductive connecting region comprising a metal-semiconductor compound, leveling a surface by chemical mechanical polishing after forming the control regions, etching-back the control regions after polishing, and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region.

    摘要翻译： 提供了一种用于制造场效应晶体管的方法。 该方法包括形成衬底区域，在衬底区域形成两个端子区域，一个端子区域是源极区域，另一个端子区域是漏极区域，形成两个电绝缘绝缘层，它们布置在 并且与控制区域相邻，形成导电连接区域，该导电连接区域将导电连接区域和基板区域导电地连接到包含金属 - 半导体化合物的导电连接区域，在形成之后通过化学机械抛光来平整表面 控制区域，在抛光之后蚀刻回控制区域，并且在蚀刻后区域，基板区域和端子区域上进行用于形成金属 - 半导体化合物的自对准方法。

    Memory device comprising select gate including carbon allotrope
    33.
    发明授权
    Memory device comprising select gate including carbon allotrope 有权
    存储器件包括选择栅极，包括碳同素异形体

    公开(公告)号：US08199560B2

    公开(公告)日：2012-06-12

    申请号：US13156370

    申请日：2011-06-09

    申请人： Ronald Kakoschke ,  Harald Seidl

    发明人： Ronald Kakoschke ,  Harald Seidl

    IPC分类号： G11C11/00

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4966

    摘要： One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope.

    摘要翻译： 一个或多个实施例涉及一种存储器件，包括：衬底; 设置在所述衬底上的栅极堆叠，所述栅极堆叠包括设置在电荷存储层上的控制栅极; 以及设置在所述衬底上并且从所述栅极堆叠横向设置的间隔物选择栅极，所述选择栅极包括碳同素异形体。

    Vertical field-effect transistor
    35.
    发明授权
    Vertical field-effect transistor 有权
    垂直场效应晶体管

    公开(公告)号：US07786530B2

    公开(公告)日：2010-08-31

    申请号：US10521528

    申请日：2003-06-12

    申请人： Ronald Kakoschke ,  Helmut Tews

    发明人： Ronald Kakoschke ,  Helmut Tews

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/66666 ,  H01L29/7827

    摘要： A vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.

    摘要翻译： 具有半导体层的垂直场效应晶体管，其中掺杂沟道区沿着凹陷布置。 “埋入”端子区域导通至半导体层的表面。 场效应晶体管还具有靠近凹陷的开口的掺杂端子区域以及远离开口的掺杂端子区域，布置在凹陷中的控制区域以及控制区域和沟道区域之间的电绝缘区域 。 远离开口的端子区域引出至包含开口的表面，或者导电地连接到通向该表面的导电连接。 控制区域仅布置在一个凹部中。 场效应晶体管是位于存储单元阵列的字线或位线处的驱动晶体管。

    MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
    36.
    发明申请
    MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF 有权
    存储器电路布置及其生产方法

    公开(公告)号：US20100210076A1

    公开(公告)日：2010-08-19

    申请号：US12772590

    申请日：2010-05-03

    申请人： Wolfgang Gruber ,  Ronald Kakoschke ,  Thomas Schwetzer ,  Dominik Wegertseder

    发明人： Wolfgang Gruber ,  Ronald Kakoschke ,  Thomas Schwetzer ,  Dominik Wegertseder

    IPC分类号： H01L21/82

    CPC分类号： G11C5/025 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

    摘要翻译： 提出了一种存储器电路装置及其制造方法，其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。

    Memory circuit arrangement and method for the production thereof
    37.
    发明授权
    Memory circuit arrangement and method for the production thereof 有权
    记忆电路装置及其生产方法

    公开(公告)号：US07764530B2

    公开(公告)日：2010-07-27

    申请号：US12258728

    申请日：2008-10-27

    申请人： Wolfgang Gruber ,  Ronald Kakoschke ,  Thomas Schwelzer ,  Dominik Wegertseder

    发明人： Wolfgang Gruber ,  Ronald Kakoschke ,  Thomas Schwelzer ,  Dominik Wegertseder

    IPC分类号： G11C5/06 ,  G11C5/02 ,  H01L21/00

    CPC分类号： G11C5/025 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

    摘要翻译： 提出了一种存储器电路装置及其制造方法，其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。