公开(公告)号：US06631086B1

公开(公告)日：2003-10-07

申请号：US10200544

申请日：2002-07-22

申请人： Colin Bill ,  Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Azrul Halim ,  Darlene G. Hamilton

发明人： Colin Bill ,  Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Azrul Halim ,  Darlene G. Hamilton

IPC分类号： G11C1606

CPC分类号： G11C29/72 ,  G11C15/00 ,  G11C16/04 ,  G11C29/16 ,  G11C29/44 ,  G11C29/48

摘要： In a method and system for repairing defective flash memory cells fabricated on a semiconductor substrate, a repair controller and a plurality of voltage sources are fabricated on the semiconductor substrate. The repair controller controls the voltage sources to apply programming voltages on respective CAM (content addressable memory) flash memory cells in a JUICE state for replacing the defective flash memory cells with a corresponding redundancy element of flash memory cells. In addition, a FAILREP logic is fabricated on the semiconductor substrate for entering a HANG state if no redundancy element of flash memory cells is available or if the defective flash memory cells have been previously repaired.

摘要翻译： 在用于修复在半导体衬底上制造的有缺陷的闪速存储器单元的方法和系统中，在半导体衬底上制造修复控制器和多个电压源。 修理控制器控制电压源以将编程电压施加在JUICE状态的相应CAM（内容可寻址存储器）闪存单元上，以用闪存单元的相应冗余元件代替有缺陷的闪存单元。 此外，如果没有闪存单元的冗余元件可用或者有缺陷的闪速存储器单元已经被修复，则在半导体衬底上制造FAILREP逻辑用于进入HANG状态。

公开(公告)号：US20090161466A1

公开(公告)日：2009-06-25

申请号：US11961772

申请日：2007-12-20

申请人： Darlene G. Hamilton ,  Mark W. Randolph ,  Don Carlos Darling ,  Ron Kornitz

发明人： Darlene G. Hamilton ,  Mark W. Randolph ,  Don Carlos Darling ,  Ron Kornitz

IPC分类号： G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C16/10 ,  G11C16/3431

摘要： Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.

摘要翻译： 本文公开了通过程序状态改写提供闪速存储器件的扩展数据保存。 作为示例，可以评估存储器单元或存储器单元组以确定单元的程序状态。 如果单元处于编程状态，与自然或非编程状态相反，则可以将充电电平，电压电平和/或类似物重写为与程序状态相关联的默认电平，而不擦除 电池第一。 因此，可以避免用于刷新需要重写和擦除的通常降低存储器单元的存储容量的小区程序状态的常规机制。 结果，存储在闪速存储器中的数据可以以减轻内存完整性损失的方式刷新，相对于可以以相对较高的速率降低存储器完整性的传统机制提供实质的益处。

公开(公告)号：US07010736B1

公开(公告)日：2006-03-07

申请号：US10200518

申请日：2002-07-22

申请人： Boon Tang Teh ,  Edward V. Bautista, Jr. ,  Ken Cheong Cheah ,  Colin Bill ,  Joseph Kucera ,  Weng Fook Lee ,  Darlene G. Hamilton

发明人： Boon Tang Teh ,  Edward V. Bautista, Jr. ,  Ken Cheong Cheah ,  Colin Bill ,  Joseph Kucera ,  Weng Fook Lee ,  Darlene G. Hamilton

IPC分类号： G01R31/28

CPC分类号： G11C29/36 ,  G11C15/00 ,  G11C16/04 ,  G11C29/12005 ,  G11C29/16 ,  G11C29/18 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/50 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/1208 ,  G11C2029/3602

摘要： An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.

摘要翻译： 在其上制造闪存单元的半导体衬底上制造地址序列器，用于在快闪存储器单元的BIST（内置自测试）期间对闪存单元进行排序。 地址排序器包括在半导体衬底上制造的地址定序器控制逻辑和地址序列器缓冲器。 地址顺序器缓冲器产生指示闪存单元的地址的多个位。 地址定序器控制逻辑控制缓冲器以通过针对多个BIST模式中的每一个的相应的位模式序列进行排序。

公开(公告)号：US06901010B1

公开(公告)日：2005-05-31

申请号：US10119366

申请日：2002-04-08

申请人： Darlene G. Hamilton ,  Eric M. Ajimine ,  Binh Le ,  Edward Hsia ,  Ken Tanpairoj

发明人： Darlene G. Hamilton ,  Eric M. Ajimine ,  Binh Le ,  Edward Hsia ,  Ken Tanpairoj

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C16/107 ,  G11C16/0475 ,  G11C16/3409 ,  G11C16/3445 ,  G11C2216/18

摘要： An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.

摘要翻译： 位于正常和互补位置的位的多位存储器阵列中的闪存单元的擦除方法。 执行正常位置中的位的擦除验证，并且如果正常位置中的位失败，并且如果还没有达到最大擦除脉冲计数，则将擦除脉冲施加到正常位和补充位。 执行补充位置中的位的擦除验证，并且如果补充位中的位失败，并且如果还没有达到最大擦除脉冲计数，则擦除脉冲将被施加到互补位和正常位位置。 如果这些位通过擦除验证，则这些位经过软编程验证。 如果这些位过高，并且如果没有达到软编程脉冲计数，则软编程脉冲将被施加到过高位。

公开(公告)号：US06771545B1

公开(公告)日：2004-08-03

申请号：US10353558

申请日：2003-01-29

申请人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

发明人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

IPC分类号： G11C1604

CPC分类号： G11C29/82 ,  G11C16/0491 ,  G11C16/3404

摘要： An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.

摘要翻译： 非易失性存储器单元的阵列包括有效的单元格列，其中数据模式可以存储在与不存储数据的损坏或非活动列相邻的位置。 存储数据模式并在其中再现数据模式的方法包括将电荷存储在活动列内的所选择的多个存储单元内。 所选择的多个存储单元表示数据模式的一部分。 识别非活动存储器单元编程模式。 非活动存储器单元编程模式识别要在其中存储电荷的所述非活动列中的所有或选定的多个存储单元，以便在存储单元的第一非活动列中周期性地存储电荷以防止过度擦除， 在批量擦除期间以及从非活性电池泄漏到相邻的活性电池。 在第一非活动列中的所选择的多个存储器单元上存储电荷。 读取在第一活动列内的每个存储单元的数据模式。

公开(公告)号：US06567303B1

公开(公告)日：2003-05-20

申请号：US10050483

申请日：2002-01-16

申请人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

发明人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445

摘要： A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

摘要翻译： 提供了一种用于以基本上高的delta VT对双位存储器单元的存储器阵列的第一和第二位进行编程的系统和方法。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 在基本上较高的增量VT下，存储器单元的第一位的编程使得第二位由于较短的通道长度而更硬更快地编程。 因此，本发明在第一和第二位的编程期间采用选择的栅极和漏极电压以及编程脉冲宽度，以确保受控的第一位VT并减慢第二位的编程。 此外，所选择的编程参数保持编程时间短而不降低电荷损耗。