公开(公告)号：US5990557A

公开(公告)日：1999-11-23

申请号：US964430

申请日：1997-11-04

Applicant: Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

Inventor： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485

CPC classification number: H01L21/02164 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/7682 ,  H01L21/76837 ,  H01L23/5222 ,  H01L2924/0002

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with void free insulating material with a dielectric constant of greater than about 3.5.

Abstract translation: 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别通过沉积具有差的绝缘材料的步进功能的非共形源（例如硅烷）而具有约0.5微米或更小的间隙 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在0.5微米或更小的空隙形成之后 间隙，沉积的非共形材料与沉积同时或顺序蚀刻，以用无空隙绝缘填充剩余的间隙。 沉积的绝缘材料的表面被平坦化为所需的厚度。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所形成的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，其中间隔为0.5或更小的导电线对之间的绝缘体的介电常数与空隙结合为至少约3或 较低，并且所有剩余的间隙都填充有绝缘材料，介电常数大于约3.5。

公开(公告)号：US5770519A

公开(公告)日：1998-06-23

申请号：US464305

申请日：1995-06-05

Applicant: Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76831 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract translation: 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属储存器。 储存器由铜的共形层或沉积在通孔上的金形成，以形成位于通孔中的铜或金塞。 在储存器和绝缘层之间设置阻挡层，以防止储存器扩散到绝缘层中。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积阻挡层和储层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和储存器。

公开(公告)号：US5691573A

公开(公告)日：1997-11-25

申请号：US481030

申请日：1995-06-07

Applicant: Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein

Inventor： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L23/52

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with the gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

Abstract translation: 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在所有导电线都已经接收到保形膜 绝缘材料和可流动的绝缘材料，优选通过蚀刻从具有约0.5微米或更小的间隙的那对导电线去除复合绝缘材料。 现在，沉积具有差的阶梯函数的非共形绝缘材料，并且在0.5微米或更小的开放间隙中产生大的空隙。 在形成空隙之后，沉积继续并且在所需的绝缘复合厚度下被平坦化。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所得到的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，导电线对之间的绝缘介电常数为0.5或更小的间隙，与空隙结合为至少约3 或更低，并且所有剩余间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

公开(公告)号：US08317910B2

公开(公告)日：2012-11-27

申请号：US12661678

申请日：2010-03-22

Applicant: Robin Cheung ,  Wen Zhong Kong

Inventor： Robin Cheung ,  Wen Zhong Kong

IPC: C23C18/42

CPC classification number: C23C18/54 ,  B32B15/018 ,  Y10T428/12875

Abstract: A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Abstract translation: 一种用于在金属结构上浸镀铂金的铂电镀溶液。 浸渍铂电镀溶液不含还原剂。 电镀工艺不需要电（例如电流），并且不需要电极（例如阳极和/或阴极）。 该溶液包括铂源和包括草酸的络合剂。 该解决方案能够将铂浸入金属表面，金属基材或其至少一部分是金属的结构。 所得的铂镀层包括厚度不超过300埃的连续的铂薄膜层。 该溶液可用于包括但不限于珠宝，医疗装置，电子结构，微电子结构，MEMS结构，纳米尺寸或更小结构，用于化学和/或催化反应的结构（例如，催化转化器））的电镀制品， 和不规则形状的金属表面。

公开(公告)号：US07393795B2

公开(公告)日：2008-07-01

申请号：US11346400

申请日：2006-02-01

Applicant: Robin Cheung ,  Siyi Li

Inventor： Robin Cheung ,  Siyi Li

IPC: H01L21/302

CPC classification number: H01L21/3105 ,  H01L21/31116 ,  H01L21/31138

Abstract: Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.

Abstract translation: 在本发明中提供了在电介质膜上进行蚀刻后沉积的方法。 在一个实施例中，该方法包括提供在蚀刻反应器中设置在其上的低k电介质层的衬底，蚀刻蚀刻反应器中的低k电介质层，以及在蚀刻的低k电介质层上形成保护层。 在另一个实施例中，该方法包括提供在蚀刻反应器中设置在其上的低k电介质层的衬底，蚀刻反应器中的低k电介质层，将蚀刻的低k电介质层与供应到 反应器，在蚀刻的低k电介质层上形成保护层，以及去除蚀刻的低k电介质层上形成的保护层。

公开(公告)号：US20070175858A1

公开(公告)日：2007-08-02

申请号：US11346400

申请日：2006-02-01

Applicant: Robin Cheung ,  Siyi Li

Inventor： Robin Cheung ,  Siyi Li

IPC: B44C1/22 ,  B05D3/00 ,  B05D3/10

CPC classification number: H01L21/3105 ,  H01L21/31116 ,  H01L21/31138

Abstract: Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.

Abstract translation: 在本发明中提供了在电介质膜上进行蚀刻后沉积的方法。 在一个实施例中，该方法包括提供在蚀刻反应器中设置在其上的低k电介质层的衬底，蚀刻蚀刻反应器中的低k电介质层，以及在蚀刻的低k电介质层上形成保护层。 在另一个实施例中，该方法包括提供在蚀刻反应器中设置在其上的低k电介质层的衬底，蚀刻反应器中的低k电介质层，将蚀刻的低k电介质层与供应到 反应器，在蚀刻的低k电介质层上形成保护层，以及去除蚀刻的低k电介质层上形成的保护层。

公开(公告)号：US06929774B2

公开(公告)日：2005-08-16

申请号：US10701387

申请日：2003-11-04

Applicant: Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

Inventor： Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

IPC: H01L21/31 ,  H01L21/00 ,  H01L21/324 ,  H01L21/677 ,  F26B7/00

CPC classification number: H01L21/67109 ,  H01L21/67115 ,  H01L21/67748

Abstract: A method and apparatus for heating and cooling a substrate are provided. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism.

Abstract translation: 提供了一种用于加热和冷却衬底的方法和装置。 提供了一种室，其包括适于加热位于加热机构附近的基板的加热机构，与加热机构间隔开并适于冷却位于冷却机构附近的基板的冷却机构，以及适于将基板 靠近加热机构的位置和靠近冷却机构的位置。

公开(公告)号：US06824666B2

公开(公告)日：2004-11-30

申请号：US10059822

申请日：2002-01-28

Applicant: Srinivas Gandikota ,  Chris R. McGuirk ,  Deenesh Padhi ,  Muhammad Atif Malik ,  Sivakami Ramanathan ,  Girish A. Dixit ,  Robin Cheung

Inventor： Srinivas Gandikota ,  Chris R. McGuirk ,  Deenesh Padhi ,  Muhammad Atif Malik ,  Sivakami Ramanathan ,  Girish A. Dixit ,  Robin Cheung

IPC: C23C2800

CPC classification number: H01L21/76843 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1831 ,  C23C18/28 ,  C23C18/30 ,  C23C18/38 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76877 ,  H01L2221/1089 ,  Y10S428/936

Abstract: An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.

Abstract translation: 一种沉积包含至少一种选自贵金属，半贵金属，其合金及其组合的金属的催化剂层的装置和方法，其形成在基板上形成的亚微米特征。 贵金属的实例包括钯和铂。 半贵金属的实例包括钴，镍和钨。 可通过无电沉积，电镀或化学气相沉积来沉积催化层。 在一个实施方案中，催化层可以沉积在特征中以用作随后沉积的导电材料的阻挡层。 在另一个实施方案中，催化剂层可以沉积在阻挡层上。 在另一个实施方案中，催化层可以沉积在沉积在阻挡层上的种子层上，以充当种子层中任何不连续性的“贴片”。 一旦沉积了催化层，可以在催化剂层上沉积诸如铜的导电材料。 在一个实施例中，导电材料通过无电沉积沉积在催化剂层上。 在另一个实施方案中，导电材料通过无电沉积然后电镀或随后进行化学气相沉积沉积在催化剂层上。 在另一个实施例中，导电材料通过电镀或化学气相沉积沉积在催化层上。

公开(公告)号：US06797620B2

公开(公告)日：2004-09-28

申请号：US10124095

申请日：2002-04-16

Applicant: John S. Lewis ,  Srinivas Gandikota ,  Sivakami Ramanathan ,  Girish Dixit ,  Robin Cheung ,  Fusen Chen

Inventor： John S. Lewis ,  Srinivas Gandikota ,  Sivakami Ramanathan ,  Girish Dixit ,  Robin Cheung ,  Fusen Chen

IPC: H01L2144

CPC classification number: H01L21/2855 ,  H01L21/76879

Abstract: A method and apparatus is provided for filling apertures formed in a substrate surface by depositing materials that selectively inhibit or limit the formation or growth of subsequent layers used to fill an aperture. In one aspect, a method is provided for processing a substrate including providing a substrate having a field and apertures formed therein, wherein the apertures each have a bottom and sidewalls, depositing a seed layer on the bottom and sidewalls of the apertures, depositing a growth-inhibiting layer on at least one of the field of the substrate or an upper portion of the sidewalls of the apertures, and depositing a conductive layer on the growth-inhibiting layer and the seed layer. Deposition of the growth-inhibiting layer improves fill of the aperture from the bottom of the aperture up to the field of the substrate.

Abstract translation: 提供了一种方法和装置，用于通过沉积选择性地抑制或限制用于填充孔的后续层的形成或生长的材料来填充形成在衬底表面中的孔。 在一个方面，提供了一种用于处理衬底的方法，包括提供具有形成在其中的场和孔的衬底，其中每个孔具有底部和侧壁，在孔的底部和侧壁上沉积种子层，沉积生长 在衬底的场中的至少一个或孔的侧壁的上部中的至少一个上的抑制层，并且在生长抑制层和种子层上沉积导电层。 生长抑制层的沉积改善了孔的填充，从孔的底部到基底的场。

公开(公告)号：US06572010B2

公开(公告)日：2003-06-03

申请号：US09880185

申请日：2001-06-12

Applicant: Yezdi N. Dordi ,  Robin Cheung

Inventor： Yezdi N. Dordi ,  Robin Cheung

IPC: B23K120

CPC classification number: H01L21/67236 ,  B23K3/0623 ,  H01L21/67225 ,  H01L21/6723

Abstract: An integrated solder bump deposition method and apparatus that enables solder bumps to be lithographically formed on a substrate. The apparatus comprises a plurality of electrolyte cells, and etch/clean/passthrough station and a reflow chamber.