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    Semiconductor processing method using high pressure liquid media treatment
    32.
    发明授权
    Semiconductor processing method using high pressure liquid media treatment 失效
    半导体加工方法采用高压液体介质处理

    公开(公告)号：US06417102B1

    公开(公告)日：2002-07-09

    申请号：US09603849

    申请日：2000-06-26

    Applicant: David A. Cathey ,  Mark Durcan

    Inventor： David A. Cathey ,  Mark Durcan

    IPC: H01L2144

    CPC classification number: H01L21/76819 ,  H01L21/7684 ,  H01L21/76882

    Abstract: In accordance with one aspect of the invention, a semiconductor processing method of treating a semiconductor wafer provides a wafer within a volume of liquid. The wafer has some electrically conductive material formed thereover. The volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere and at a temperature of at least 200° C. and below and within 10% of the melting point of the electrically conductive material. In accordance with another aspect, the volume of liquid within the chamber with the wafer therein is established at a pressure of greater than 1 atmosphere. After establishing the pressure of greater than 1 atmosphere, the pressure of the volume of liquid is lowered to a point effective to vaporize said liquid and the vapor is withdrawn from the chamber. In accordance with still another aspect, a semiconductor processing method of increasing planarity of an outer surface on a substrate comprises exposing the outer surface to a volume of liquid at a pressure of greater than about 200 atmospheres. The invention has particular utility to more completely filling contact openings with electrically conductive material, and to increasing substrate planarity. A typical preferred treatment is expected to last anywhere from seconds up to ten minutes or more.

    Abstract translation: 根据本发明的一个方面，处理半导体晶片的半导体处理方法在一定体积的液体内提供晶片。 该晶片具有形成在其上的一些导电材料。 在其中具有晶片的腔室内的液体体积建立在大于1大气压的压力下，并且在至少200℃的温度以及导电材料的熔点的低于和低于10％的温度下。 根据另一方面，其中具有晶片的腔室内的液体体积建立在大于1个大气压的压力下。 在建立大于1个大气压力之后，将液体体积的压力降低到有效蒸发所述液体的一个点，并且蒸气从室中排出。 根据另一方面，一种增加衬底上的外表面的平面度的半导体加工方法包括将外表面暴露于大于约200大气压的压力下的一定体积的液体。 本发明特别有用于更完全地用导电材料填充接触开口，并且增加衬底平面度。 预期典型的优选治疗将持续从几秒到十分钟或更长。

    Matrix addressable display with electrostatic discharge protection
    34.
    发明授权
    Matrix addressable display with electrostatic discharge protection 失效
    具有静电放电保护的矩阵可寻址显示

    公开(公告)号：US06356250B1

    公开(公告)日：2002-03-12

    申请号：US09640826

    申请日：2000-08-16

    Applicant: David A. Cathey ,  Glen E. Hush ,  Manny K. F. Ma ,  Craig M. Dunham ,  David A. Zimlich

    Inventor： David A. Cathey ,  Glen E. Hush ,  Manny K. F. Ma ,  Craig M. Dunham ,  David A. Zimlich

    IPC: G09G328

    CPC classification number: H01J31/127 ,  H01J3/022 ,  H01J2201/319 ,  H01J2329/92

    Abstract: A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and a first reference potential or between row lines and a second reference potential. The diodes provide a current path to discharge static voltage and thereby prevent a high voltage differential from being maintained between the emitter sets and the extraction grids. The diodes thereby prevent the emitter sets from emitting electrons at a high rate that may damage or destroy the emitter sets. In one embodiment, the diodes are coupled directly between the grid sections and the row lines. In one embodiment, the diodes are formed in an insulative layer carrying the grid sections. In another embodiment, the diodes are integrated into the emitter substrate.

    Abstract translation: 场发射显示器包括耦合到发射极衬底和提取栅极的静电放电保护电路。 在优选实施例中，静电放电电路包括在网格部分和第一参考电位之间或在行线和第二参考电位之间反向偏置的二极管。 二极管提供电流路径来放电静电压，从而防止在发射极组和提取栅之间保持高电压差。 因此，二极管可防止发射极组以可能损坏或破坏发射极组的高速率发射电子。 在一个实施例中，二极管直接连接在网格部分和行线之间。 在一个实施例中，二极管形成在承载网格部分的绝缘层中。 在另一个实施例中，二极管被集成到发射器衬底中。

    Method of forming an array of emitter tips
    35.
    发明授权
    Method of forming an array of emitter tips 失效
    形成发射器尖端阵列的方法

    公开(公告)号：US6165374A

    公开(公告)日：2000-12-26

    申请号：US354529

    申请日：1999-07-15

    Applicant: David A. Cathey ,  Kevin Tjaden

    Inventor： David A. Cathey ,  Kevin Tjaden

    IPC: H01J9/02 ,  B44C1/22 ,  H01L21/00

    CPC classification number: H01J9/025 ,  H01J2201/30403

    Abstract: A method for fabricating sharp asperities. A substrate is provided which has a mask layer disposed thereon, and a layer of micro-spheres is disposed superjacent the mask layer. The micro-spheres are for patterning the mask layer. Portions of the mask layer are selectively removed, thereby forming circular masks. The substrate is isotropically etched, thereby creating sharp asperities.

    Abstract translation: 一种制造尖锐凹凸的方法。 提供了具有设置在其上的掩模层的基板，并且在该掩模层的上方布置一层微球。 微球用于图案化掩模层。 选择性地去除掩模层的一部分，从而形成圆形掩模。 基板被各向同性地蚀刻，从而产生尖锐的凹凸。

    Method of increasing capacitance by surface roughening in semiconductor wafer processing
    36.
    发明授权
    Method of increasing capacitance by surface roughening in semiconductor wafer processing 失效
    通过半导体晶片加工中的表面粗糙度增加电容的方法

    公开(公告)号：US6074926A

    公开(公告)日：2000-06-13

    申请号：US813913

    申请日：1997-03-07

    Applicant: David A. Cathey ,  Mark E. Tuttle ,  Tyler A. Lowrey

    Inventor： David A. Cathey ,  Mark E. Tuttle ,  Tyler A. Lowrey

    IPC: H01L21/02 ,  H01L21/334 ,  H01L21/70

    CPC classification number: H01L28/84 ,  H01L29/66181 ,  Y10S438/964

    Abstract: A method of increasing capacitance by surface roughening in semiconductor wafer processing includes the following steps: a) applying a first layer of material atop a substrate thereby defining an exposed surface; b) incontinuously adhering discrete solid particles to the first layer exposed surface to roughen the exposed surface; and c) applying a second layer of material atop the first layer and adhered solid particles to define an outer surface, the particles adhered to the first layer inducing roughness into the outer surface thereby increasing its surface area and accordingly capacitance of the second layer in the final wafer structure.

    Abstract translation: 通过在半导体晶片处理中通过表面粗糙度增加电容的方法包括以下步骤：a）在基板顶部施加第一层材料，从而限定暴露的表面; b）不连续地将离散的固体颗粒粘附到第一层暴露表面以使暴露的表面粗糙; 以及c）在第一层上方施加第二层材料并粘附固体颗粒以限定外表面，粘附到第一层的颗粒引起粗糙度进入外表面，从而增加其表面积，从而增加其中的第二层的电容 最终的晶圆结构。

    Etch stop for use in etching of silicon oxide
    39.
    发明授权
    Etch stop for use in etching of silicon oxide 失效
    蚀刻停止用于蚀刻氧化硅

    公开(公告)号：US6013943A

    公开(公告)日：2000-01-11

    申请号：US850461

    申请日：1997-05-05

    Applicant: David A. Cathey ,  J. Brett Rolfson ,  Valerie A. Ward ,  Karen M. Winchester

    Inventor： David A. Cathey ,  J. Brett Rolfson ,  Valerie A. Ward ,  Karen M. Winchester

    IPC: H01L21/311 ,  H01L21/318 ,  H01L23/58

    CPC classification number: H01L21/31116 ,  H01L21/3185 ,  Y10S438/97

    Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, O--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH.sub.3 flow, decreasing the SiH.sub.4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.

    Abstract translation: 用于氧化硅干氟蚀刻工艺中的蚀刻停止层由氮化物制成，其中以氢键连接在其中，其形式为N-H键，O-H键或截留的游离氢。 蚀刻停止层是通过在标准PECVD氮化硅制造工艺中增加NH 3流，降低SiH4流量，降低氮气流量或全部三种来制备的。 替代地，蚀刻停止可以通过在PECVD工艺或LPCVD工艺中脉冲RF场来制造。

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