公开(公告)号：US07709327B2

公开(公告)日：2010-05-04

申请号：US11724575

申请日：2007-03-14

申请人： David H. Wells

发明人： David H. Wells

IPC分类号： H01L21/336

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

摘要： Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

摘要翻译： 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。

公开(公告)号：US07625776B2

公开(公告)日：2009-12-01

申请号：US11445911

申请日：2006-06-02

申请人： David H. Wells ,  H. Montgomery Manning

发明人： David H. Wells ,  H. Montgomery Manning

IPC分类号： H01L21/00

CPC分类号： H01L21/3065 ,  H01L21/76232 ,  H01L21/76283

摘要： A method of forming at least one undercut structure in a semiconductor substrate. The method comprises providing a semiconductor substrate, forming at least one doped region in the semiconductor substrate, and removing the at least one doped region to form at least one undercut structure in the semiconductor substrate. The at least one undercut structure may include at least one substantially vertical shelf, at least one substantially horizontal shelf, and at least one faceted surface. The at least one doped region may be formed by implanting an impurity in the semiconductor substrate, which is, optionally, annealed. The at least one doped region may be removed selective to the undoped portion of the semiconductor substrate by at least one of wet etching or dry etching. An intermediate semiconductor structure that comprises a single crystalline silicon substrate and at least one undercut structure formed in the single crystalline silicon substrate is also disclosed.

摘要翻译： 一种在半导体衬底中形成至少一个底切结构的方法。 所述方法包括提供半导体衬底，在所述半导体衬底中形成至少一个掺杂区域，以及移除所述至少一个掺杂区域以在所述半导体衬底中形成至少一个底切结构。 至少一个底切结构可以包括至少一个基本上垂直的搁架，至少一个基本上水平的搁架和至少一个小面。 可以通过在半导体衬底中注入杂质来形成至少一个掺杂区域，该衬底可选择地退火。 至少一个掺杂区域可以通过湿式蚀刻或干蚀刻中的至少一种来选择性地移除到半导体衬底的未掺杂部分。 还公开了包括单晶硅衬底和形成在单晶硅衬底中的至少一个底切结构的中间半导体结构。

公开(公告)号：US07504298B2

公开(公告)日：2009-03-17

申请号：US11711569

申请日：2007-02-26

申请人： H. Montgomery Manning ,  David H. Wells

发明人： H. Montgomery Manning ,  David H. Wells

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10823

摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.

摘要翻译： 存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。 数字线与相邻的存储器单元耦合，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。 形成存储单元的方法包括在衬底中形成掩埋的数字线，并且在与衬底数字线紧邻的衬底中形成垂直柱。 双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。

公开(公告)号：US20080188073A1

公开(公告)日：2008-08-07

申请号：US11724654

申请日：2007-03-14

申请人： David H. Wells

发明人： David H. Wells

IPC分类号： H01L21/768

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

摘要： Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

摘要翻译： 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。

公开(公告)号：US20080185647A1

公开(公告)日：2008-08-07

申请号：US11724575

申请日：2007-03-14

申请人： David H. Wells

发明人： David H. Wells

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/84

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

摘要： Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

摘要翻译： 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。

公开(公告)号：US07396781B2

公开(公告)日：2008-07-08

申请号：US11150408

申请日：2005-06-09

申请人： David H. Wells

发明人： David H. Wells

IPC分类号： H01L21/00

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76838 ,  H01L27/105 ,  Y10S438/946 ,  Y10S438/947

摘要： Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sideswalls. The critical dimension of the spacers is selected based upon the sidewall positions, so that the spacers are centered at desired positions. The mandrels are removed and the spacers are used as mandrels for a subsequent spacer formation. A second material is then deposited on the first set of spacers, with the critical dimensions of the second set of spacers chosen so that these spacers are also centered at their desired positions. The first set of spacers is removed and the second set is used as a mask for etching a substrate. By selecting the critical dimensions of spacers based partly on the measured position of mandrels, the pitch of the spacers can be finely controlled.

摘要翻译： 通过分开形成至少两组间隔物来最小化使用间距倍增形成的特征的间距的变化。 形成心轴并测量其侧壁的位置。 第一组间隔件形成在侧壁上。 基于侧壁位置选择间隔物的临界尺寸，使得间隔件居中在期望的位置。 去除心轴，并且间隔件用作后续间隔物形成的心轴。 然后将第二材料沉积在第一组间隔物上，其中第二组间隔物的临界尺寸选择为使得这些间隔物也位于其所需位置的中心。 去除第一组间隔物，将第二组用作蚀刻基底的掩模。 通过部分地基于心轴的测量位置选择间隔物的临界尺寸，可以精细地控制间隔物的间距。

公开(公告)号：US20070281493A1

公开(公告)日：2007-12-06

申请号：US11445544

申请日：2006-06-02

申请人： Janos Fucsko ,  David H. Wells ,  Patrick Flynn ,  Whonchee Lee

发明人： Janos Fucsko ,  David H. Wells ,  Patrick Flynn ,  Whonchee Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/30608 ,  H01L21/302 ,  H01L21/31116 ,  H01L21/76232 ,  H01L29/66818

摘要： A single crystal silicon etching method includes providing single crystal silicon substrate having at least one trench therein. The substrate is exposed to an anisotropic etchant which undercuts the silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

摘要翻译： 单晶硅蚀刻方法包括提供在其中具有至少一个沟槽的单晶硅衬底。 将衬底暴露于削弱硅的各向异性蚀刻剂。 通过控制蚀刻的长度，可以产生单晶硅中的单晶硅岛或平滑的垂直壁。

公开(公告)号：US20070278183A1

公开(公告)日：2007-12-06

申请号：US11445718

申请日：2006-06-02

申请人： Whonchee Lee ,  Janos Fucsko ,  David H. Wells

发明人： Whonchee Lee ,  Janos Fucsko ,  David H. Wells

IPC分类号： B44C1/22 ,  C03C15/00

CPC分类号： H01L21/30608 ,  B81B2203/033 ,  B81B2203/0338 ,  B81C1/00626 ,  C30B29/06 ,  C30B33/10

摘要： A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the direction. The resulting structure includes an undercut feature when patterned in the direction.

摘要翻译： 单晶硅蚀刻方法包括提供其中具有至少一个沟槽的单晶硅衬底。 将衬底暴露于缓冲的氟化物蚀刻溶液，其在<100>方向图案化时，其将硅切割以提供横向搁板。 当沿<100>方向图案化时，所得结构包括底切特征。

公开(公告)号：US07161211B2

公开(公告)日：2007-01-09

申请号：US10289550

申请日：2002-11-06

申请人： Kanwal K. Raina ,  David H. Wells

发明人： Kanwal K. Raina ,  David H. Wells

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/392 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L21/2855 ,  C23C14/0057 ,  C23C14/185 ,  H01L21/32051 ,  H01L29/458 ,  H01L29/4908 ,  Y10S438/937 ,  Y10T428/12229

摘要： Aluminum-containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum or aluminum alloys onto a semiconductor substrate. The aluminum-containing film so formed is hillock-free and has low resistivity, relatively low roughness compared to pure aluminum, good mechanical strength, and low residual stress.

摘要翻译： 含有膜的含氧膜含铝。 在铝或铝合金溅射沉积到半导体衬底上时，通过将氢气与氩气一起引入溅射沉积真空室中形成含铝膜。 这样形成的含铝膜与纯铝相比具有低电阻率，较低的粗糙度，良好的机械强度和较低的残余应力。

公开(公告)号：US06391670B1

公开(公告)日：2002-05-21

申请号：US09303091

申请日：1999-04-29

申请人： David H. Wells ,  Ji Ung Lee ,  Aaron R. Wilson

发明人： David H. Wells ,  Ji Ung Lee ,  Aaron R. Wilson

IPC分类号： H01L2100

CPC分类号： H01J29/467 ,  H01J9/025 ,  H01J2329/00

摘要： A method of forming an extraction grid for field emitter tip structures is described. A conductive layer is deposited over an insulative layer formed over the field emitter tip structures. The conductive layer is milled using ion milling. Owing to topographical differences along an exposed surface of the conductive layer, ions strike the exposed surface at various angles of incidence. As etch rate from ion milling is dependent at least in part upon angle of incidence, a selectivity based on varying topography of the exposed surface (“topographic selectivity”) results in non-uniform removal of material thereof. In particular, portions of the conductive layer in near proximity to the field emitter tip structures are removed faster than portions of the conductive layer between emitter tip structures. Thus, portions of the insulative layer in near proximity to the field emitter tip structures may be exposed while leaving intervening portions of the conductive layer for forming the extraction grid. Accordingly, such formation of the extraction grid is self-aligned to its associated emitter tip structures.

摘要翻译： 描述了一种形成场发射器尖端结构的提取栅格的方法。 导电层沉积在形成在场致发射极尖端结构之上的绝缘层上。 使用离子铣削铣削导电层。 由于沿着导电层的暴露表面的形貌差异，离子以不同的入射角度撞击暴露的表面。 由于来自离子研磨的蚀刻速率至少部分地取决于入射角，基于暴露表面的变化的形貌的选择性（“地形选择性”）导致其材料的非均匀去除。 特别地，与发射极尖端结构之间的导电层的部分相比，导电层在场发射极尖端结构附近的部分被去除得更快。 因此，靠近场发射极尖端结构的绝缘层的部分可以暴露，同时留下用于形成提取栅格的导电层的中间部分。 因此，提取栅格的这种形成与其相关联的发射极尖端结构自对准。