公开(公告)号：US20060019443A1

公开(公告)日：2006-01-26

申请号：US10710566

申请日：2004-07-21

申请人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

发明人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Hiroyuki Akatsu ,  George Worth ,  Jay Strane ,  Byeong Kim

IPC分类号： H01L21/467 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L27/10841 ,  H01L27/10897

摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.

摘要翻译： 通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部 氧化物晚期过程。 新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。 还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

公开(公告)号：US09059000B2

公开(公告)日：2015-06-16

申请号：US12106586

申请日：2008-04-21

申请人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

发明人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  G03F7/11

CPC分类号： H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

公开(公告)号：US08624331B2

公开(公告)日：2014-01-07

申请号：US12659644

申请日：2010-03-16

申请人： Deok-kee Kim ,  Choong-rae Cho

发明人： Deok-kee Kim ,  Choong-rae Cho

IPC分类号： H01L29/76

CPC分类号： H01L45/146 ,  H01L27/249 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1666

摘要： A non-volatile memory device includes: at least one horizontal electrode; at least one vertical electrode disposed to intersect the at least one horizontal electrode at an intersection region; at least one data layer disposed at the intersection region and having a conduction-insulation transition property; and at least one anti-fuse layer connected in series with the at least one data layer.

摘要翻译： 非易失性存储器件包括：至少一个水平电极; 至少一个垂直电极，设置成在交叉区域与所述至少一个水平电极相交; 至少一个数据层设置在交叉区域并具有导电绝缘转移特性; 以及与所述至少一个数据层串联连接的至少一个反熔丝层。

公开(公告)号：US08349665B2

公开(公告)日：2013-01-08

申请号：US12929205

申请日：2011-01-07

申请人： Deok-kee Kim

发明人： Deok-kee Kim

IPC分类号： H01H37/76

CPC分类号： G11C17/16

摘要： A fuse device includes a fuse unit, which includes a cathode, an anode, and a fuse link coupling the cathode and the anode. A transistor includes at least a portion of the fuse unit to be used as an element of the transistor.

公开(公告)号：US07723820B2

公开(公告)日：2010-05-25

申请号：US11616965

申请日：2006-12-28

申请人： Deok-kee Kim ,  Byeongju Park ,  John M. Safran

发明人： Deok-kee Kim ,  Byeongju Park ,  John M. Safran

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C17/18 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides structures for an integrated antifuse that incorporates an integrated sensing transistor with an integrated heater. Two terminals connected to the upper plate allow the heating of the upper plate, accelerating the breakdown of the antifuse dielectric at a lower bias voltage. Part of the upper plate also serves as the gate of the integrated sensing transistor. The antifuse dielectric serves as the gate dielectric of the integrated transistor. The lower plate comprises a channel, a drain, and a source of a transistor. While intact, the integrated sensing transistor allows a passage of transistor current through the drain. When programmed, the antifuse dielectric, which is the gate of the integrated transistor, is subjected to a gate breakdown, shorting the gate to the channel and resulting in a decreased drain current. The integrated antifuse structure can also be wired in an array to provide a compact OTP memory array.

摘要翻译： 本发明提供了一种集成反熔丝的结构，该结构集成了具有集成加热器的集成感测晶体管。 连接到上板的两个端子允许上板的加热，加速在更低偏压下的反熔丝电介质的击穿。 上板的一部分也用作集成感测晶体管的栅极。 反熔丝电介质用作集成晶体管的栅极电介质。 下板包括晶体管的沟道，漏极和源极。 虽然完整，集成感测晶体管允许晶体管电流通过漏极。 当编程时，作为集成晶体管的栅极的反熔丝电介质受到栅极击穿，使栅极短路到沟道并导致漏极电流降低。 集成的反熔丝结构也可以以阵列布线，以提供紧凑的OTP存储器阵列。

公开(公告)号：US20090302417A1

公开(公告)日：2009-12-10

申请号：US12136246

申请日：2008-06-10

申请人： Deok-kee Kim ,  Ahmet S. Ozcan ,  Haining S. Yang

发明人： Deok-kee Kim ,  Ahmet S. Ozcan ,  Haining S. Yang

IPC分类号： H01L23/525 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An e-fuse structure and method has anode, a fuse link, and a cathode. The first end of the fuse link is connected to the anode and the second end of the fuse link opposite the first end is connected to the cathode. This structure also includes a first silicide layer on the anode and the fuse link and a second silicide layer, different than the first silicide layer, on the cathode. The difference between the first silicide layer and the second silicide layer causes an enhanced flux divergence region at the second end of the fuse link.

摘要翻译： 电熔丝结构和方法具有阳极，熔丝链和阴极。 熔丝链的第一端连接到阳极，并且与第一端相对的熔丝连接的第二端连接到阴极。 该结构还包括阴极上的阳极和熔丝链上的第一硅化物层和不同于第一硅化物层的第二硅化物层。 第一硅化物层和第二硅化物层之间的差异在熔丝链的第二端引起增强的磁通发散区域。

公开(公告)号：US20090256624A1

公开(公告)日：2009-10-15

申请号：US12385391

申请日：2009-04-07

申请人： Deok-kee Kim ,  Jung-Hun Sung ,  Sang-moo Choi ,  Soo-Jung Hwang

发明人： Deok-kee Kim ,  Jung-Hun Sung ,  Sang-moo Choi ,  Soo-Jung Hwang

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01H85/00 ,  H01L23/525

CPC分类号： H01L23/5252 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an antifuse and methods of operating and manufacturing the same. The antifuse may include first and second conductors separate from each other; a dielectric layer for an antifuse between the first and second conductors; and a diffusion layer between one of the first and second conductors and the dielectric layer.

摘要翻译： 提供反熔丝及其操作和制造方法。 反熔丝可以包括彼此分离的第一和第二导体; 用于第一和第二导体之间的反熔丝的电介质层; 以及在第一和第二导体之一和介电层之间的扩散层。

公开(公告)号：US20090096060A1

公开(公告)日：2009-04-16

申请号：US12216094

申请日：2008-06-30

申请人： Deok-kee Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  I-hun Song ,  Won-joo Kim ,  Young-gu Jin ,  Hyuk-soon Choi ,  Suk-pil Kim

发明人： Deok-kee Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  I-hun Song ,  Won-joo Kim ,  Young-gu Jin ,  Hyuk-soon Choi ,  Suk-pil Kim

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.

摘要翻译： 提供了防泡结构，反熔丝阵列，制造方法和操作方法。 反熔丝结构包括在半导体衬底内形成为第一扩散区的位线，形成在位线上的绝缘层，以及形成在绝缘层上的字线。 反熔丝阵列包括排列成阵列的多个反熔丝结构。

公开(公告)号：US20090057818A1

公开(公告)日：2009-03-05

申请号：US11847379

申请日：2007-08-30

申请人： Deok-kee Kim ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

发明人： Deok-kee Kim ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.

摘要翻译： 一种电可编程保险丝，包括阴极构件，阳极构件和连接构件，其中所述阴极构件，所述阳极构件和所述连接构件各自包括可操作地定位所述可编程熔丝中的感应电迁移的多种材料中的一种。

公开(公告)号：US07485910B2

公开(公告)日：2009-02-03

申请号：US10907630

申请日：2005-04-08

申请人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dae-Gyu Park

发明人： Deok-kee Kim ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dae-Gyu Park

IPC分类号： H01L27/108

CPC分类号： H01L27/12 ,  H01L27/10841 ,  H01L27/10891

摘要： The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides methods that are capable of forming the inventive semiconductor structure.

摘要翻译： 本发明提供一种半导体结构，其包括位于半导体存储器件上方的有源字线和位于所述有源字线附近并位于衬底的有效区域之上的被动字线。 根据本发明，被动字线通过衬垫氮化物与有源区分离。 本发明还提供了能够形成本发明的半导体结构的方法。