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    Multi-bit memory device using multi-plug
    3.
    发明授权
    Multi-bit memory device using multi-plug 有权
    多位存储设备使用多插头

    公开(公告)号：US07929330B2

    公开(公告)日：2011-04-19

    申请号：US12379894

    申请日：2009-03-04

    申请人： Deok-kee Kim ,  Ha-young You ,  Young-chang Joo ,  Jung-hun Sung ,  Soo-jung Hwang ,  Sung-yup Jung

    发明人： Deok-kee Kim ,  Ha-young You ,  Young-chang Joo ,  Jung-hun Sung ,  Soo-jung Hwang ,  Sung-yup Jung

    IPC分类号： G11C17/06

    CPC分类号： H01L27/101 ,  G11C11/5692

    摘要： A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode may be located in a position higher than that of the cathode. Also, the cathode, the anode, the link, and the first connection element may be formed on the same plane.

    摘要翻译： 存储器件可以包括阴极，阳极，连接到阳极的连杆以及将连杆连接到阴极的第一连接元件。 连接件和阳极可以位于比阴极或连接件低的位置，并且阳极可以位于比阴极高的位置。 此外，阴极，阳极，连接件和第一连接元件也可以形成在同一平面上。

    Electrical fuse device including a fuse link
    6.
    发明申请
    Electrical fuse device including a fuse link 审中-公开
    电熔丝装置包括熔断体

    公开(公告)号：US20090206978A1

    公开(公告)日：2009-08-20

    申请号：US12379347

    申请日：2009-02-19

    申请人： Soo-Jung Hwang ,  Deok-kee Kim ,  Jung-hun Sung ,  I-hun Song ,  Hyuk-soon Choi

    发明人： Soo-Jung Hwang ,  Deok-kee Kim ,  Jung-hun Sung ,  I-hun Song ,  Hyuk-soon Choi

    IPC分类号： H01H85/10

    CPC分类号： G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Example embodiments relate to an electrical device, for example, to an electrical fuse device that includes a fuse link for linking a cathode and anode. An electrical device may include a cathode, an anode, and a fuse link. The fuse link may link the cathode and the anode. The fuse link may include a multi-metal layer structure. The fuse link may include a first metal layer including a first resistance, and a second metal layer stacked on the first metal layer and including a second resistance. The first resistance may be different from the second resistance. The fuse link may include a weak point as a region at which electrical blowing is performed easier than other regions of the fuse link.

    摘要翻译： 示例性实施例涉及电气设备，例如电气熔断器件，其包括用于连接阴极和阳极的熔断体。 电气设备可以包括阴极，阳极和熔断体。 熔丝链可以连接阴极和阳极。 熔丝链可以包括多金属层结构。 熔丝连接件可以包括第一金属层和第二金属层，第一金属层包括第一电阻，第二金属层堆叠在第一金属层上并包括第二电阻。 第一阻力可能与第二阻力不同。 熔断体可以包括作为进行电吹送的区域的弱点比熔丝链的其它区域更容易。

    Variable resistance memory device with trigger circuit for set/reset write operations
    7.
    发明授权
    Variable resistance memory device with trigger circuit for set/reset write operations 有权
    可变电阻存储器件，具有用于置位/复位写入操作的触发电路

    公开(公告)号：US08559207B2

    公开(公告)日：2013-10-15

    申请号：US13009077

    申请日：2011-01-19

    申请人： Deok-kee Kim ,  Ho Jung Kim

    发明人： Deok-kee Kim ,  Ho Jung Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2213/72

    摘要： A variable resistance memory device comprises a variable resistance memory cell, a switch that selectively passes a write voltage to an input terminal of the variable resistance memory cell, and a trigger circuit that controls the switch to cut off the write voltage from the input terminal upon determining that the variable resistance memory cell is programmed to a target state by detecting voltage fluctuation of the one side of variable resistance memory cell.

    摘要翻译： 可变电阻存储器件包括可变电阻存储单元，选择性地将写入电压传递到可变电阻存储单元的输入端的开关，以及触发电路，其控制开关从输入端截取写入电压， 通过检测可变电阻存储单元的一侧的电压波动来确定可变电阻存储单元被编程为目标状态。

    Variable resistance memory device and related method of operation
    8.
    发明授权
    Variable resistance memory device and related method of operation 有权
    可变电阻存储器件及相关操作方法

    公开(公告)号：US08526258B2

    公开(公告)日：2013-09-03

    申请号：US13026456

    申请日：2011-02-14

    申请人： Deok-kee Kim ,  Ho Jung Kim

    发明人： Deok-kee Kim ,  Ho Jung Kim

    IPC分类号： G11C7/02

    CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071

    摘要： A variable resistance memory device comprises a memory cell comprising a variable resistance device and a select transistor connected in series to the variable resistance device. The variable resistance memory device further comprises a write driver for supplying a write voltage to opposite sides of the memory cell, and a feedback circuit for detecting a resistance change of the variable resistance device and controlling a gate voltage of the select transistor according to the detected resistance change.

    摘要翻译： 可变电阻存储器件包括存储单元，该存储单元包括与可变电阻器件串联连接的可变电阻器件和选择晶体管。 可变电阻存储器件还包括写入驱动器，用于向存储单元的相对侧提供写入电压;以及反馈电路，用于检测可变电阻器件的电阻变化，并根据检测到的来控制选择晶体管的栅极电压 阻力变化。

    Nonvolatile memory device
    9.
    发明授权
    Nonvolatile memory device 有权
    非易失性存储器件

    公开(公告)号：US08247788B2

    公开(公告)日：2012-08-21

    申请号：US12659175

    申请日：2010-02-26

    申请人： Kwang-soo Seol ,  Yoon-dong Park ,  Deok-kee Kim ,  Sang-jun Choi

    发明人： Kwang-soo Seol ,  Yoon-dong Park ,  Deok-kee Kim ,  Sang-jun Choi

    IPC分类号： H01L45/00

    CPC分类号： H01L27/2445 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    摘要： The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.

    摘要翻译： 非易失性存储器件包括至少一对第一电极线，设置在至少一对第一电极线之间的至少一个器件结构和设置在该至少一个器件结构与至少一对第一电极线之间的电介质层 电极线。 所述至少一个器件结构包括第二电极线，所述第二电极线包括第一导电类型半导体，与所述第二电极线相邻的电阻改变材料层，与所述电阻变化材料层相邻的通道，并且包括不同于所述第一导电类型的第一导电型半导体 导电型半导体和与沟道相邻的第三电极线，并且包括第一导电型半导体。