公开(公告)号：US5586276A

公开(公告)日：1996-12-17

申请号：US301313

申请日：1994-09-06

Applicant: Edward Grochowski ,  Kenneth Shoemaker

Inventor： Edward Grochowski ,  Kenneth Shoemaker

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/00

CPC classification number: G06F9/30152 ,  G06F9/3816 ,  G06F9/3885

Abstract: Apparatus for determining the length of an instruction being processed by a computer system when instructions vary in length and appear sequentially in an instruction stream without differentiation between instructions including apparatus for providing an end bit for each predesignated length of an instruction to indicate that the instruction ends at that point in its length, apparatus for setting the end bit at the particular predesignated length of the instruction which is the actual end of the instruction, a first channel for processing a first instruction in sequence, a second channel for processing an instruction next following the first instruction, and apparatus for looking at the end bits of an instruction being processed by the first channel to determine the end point of that instruction and the beginning of the next instruction from the stream of instructions.

Abstract translation: 用于当指令长度变化并且顺序地出现在指令流中时确定由计算机系统处理的指令的长度的装置，而不区分指令，包括用于为指令的每个预定指定长度提供结束位的装置，以指示指令结束 在其长度的那一点上，用于将作为指令的实际结束的指令的特定预定长度的结束位设置用于依次处理第一指令的第一通道，用于处理下一个指令的第二通道 第一指令和用于查看由第一通道正在处理的指令的结束位的装置，以从指令流确定该指令的终点和下一个指令的开始。

公开(公告)号：US20170192904A1

公开(公告)日：2017-07-06

申请号：US15384067

申请日：2016-12-19

Applicant: Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/1009 ,  G06F12/109 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/152 ,  G06F2212/6032 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/68

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US08601242B2

公开(公告)日：2013-12-03

申请号：US12653800

申请日：2009-12-18

Applicant: Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

Inventor： Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

IPC: G06F9/00

CPC classification number: G06F9/3004 ,  G06F9/30087

Abstract: A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.

Abstract translation: 公开了一种执行快速比较交换操作的技术。 更具体地，描述了实现快速比较交换操作以及启用快速比较交换操作的高速缓存行标记操作的机器可读介质，处理器和系统。

公开(公告)号：US07315920B2

公开(公告)日：2008-01-01

申请号：US11028293

申请日：2005-01-04

Applicant: Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F12/00

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

公开(公告)号：US20060100840A1

公开(公告)日：2006-05-11

申请号：US11317948

申请日：2005-12-23

Applicant: Edward Grochowski ,  David Sager ,  Vivek Tiwari ,  Ian Young ,  David Ayers

Inventor： Edward Grochowski ,  David Sager ,  Vivek Tiwari ,  Ian Young ,  David Ayers

IPC: G06F17/50

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5036 ,  G06F2217/78 ,  Y02D10/172

Abstract: A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

公开(公告)号：US20060095807A1

公开(公告)日：2006-05-04

申请号：US10952627

申请日：2004-09-28

Applicant: Edward Grochowski ,  John Shen ,  Hong Wang ,  Doron Orenstein ,  Gad Sheaffer ,  Ronny Ronen ,  Murali Annavaram

Inventor： Edward Grochowski ,  John Shen ,  Hong Wang ,  Doron Orenstein ,  Gad Sheaffer ,  Ronny Ronen ,  Murali Annavaram

IPC: G06F1/30

CPC classification number: G06F9/3851 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/3897 ,  Y02D10/16 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.

Abstract translation: 公开了一种用于改变多核处理器的配置的方法和装置。 在一个实施例中，节气门模块（或节气门逻辑）可以确定当前执行的程序中存在的并行度量，并且改变该程序在各种核心上的线程的执行。 如果并行量高，则处理器可以被配置为在被配置为消耗较少功率的核上运行更大量的线程。 如果并行量较低，则处理器可能被配置为在配置为更高标量性能的核心上运行较少量的线程。

公开(公告)号：US20050223199A1

公开(公告)日：2005-10-06

申请号：US10816103

申请日：2004-03-31

Applicant: Edward Grochowski ,  Hong Wang ,  John Shen ,  Perry Wang ,  Jamison Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

Inventor： Edward Grochowski ,  Hong Wang ,  John Shen ,  Perry Wang ,  Jamison Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/44

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Abstract translation: 公开了提供用户级多线程的方法和系统。 根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。 一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

公开(公告)号：US20050216714A1

公开(公告)日：2005-09-29

申请号：US10809957

申请日：2004-03-25

Applicant: Edward Grochowski

Inventor： Edward Grochowski

IPC: G06F9/00 ,  G06F9/38

CPC classification number: G06F9/3863 ,  G06F9/30072 ,  G06F9/3842 ,  G06F9/3848

Abstract: A method and apparatus for making predictions which give a predicted value and also a confidence value is presented. In one embodiment, a global confidence history is maintained. The global confidence history may be hashed with an instruction pointer to form an index into a pattern history table or tables that include local histories of confidence values and predicted values. The outputs of the pattern history tables may be used to form confidence values and predicted values.

Abstract translation: 提出了一种提供预测值和置信度值的预测方法和装置。 在一个实施例中，保持全局置信历史。 全局置信历史可以用指令指针进行散列，以形成包含置信值和预测值的局部历史的模式历史表或表的索引。 模式历史表的输出可以用于形成置信度值和预测值。

公开(公告)号：US20050120184A1

公开(公告)日：2005-06-02

申请号：US11028293

申请日：2005-01-04

Applicant: Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

公开(公告)号：US06754689B2

公开(公告)日：2004-06-22

申请号：US09745697

申请日：2000-12-22

Applicant: Bharat Bhushan ,  Edward Grochowski ,  John Crawford

Inventor： Bharat Bhushan ,  Edward Grochowski ,  John Crawford

IPC: G06F750

CPC classification number: G06F7/50 ,  G06F7/4824

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing an adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit to generate a valid outcome in redundant form of a subtraction operation. A carry-save adder structure is used in one preferred embodiment of the current invention to perform a subtraction operation A−B, where B is a number represented by one of its valid carry-sum redundant representations. In order to perform the subtraction operation, each of the carry bits and each of the sum bits in a redundant representation of B are complemented and supplied to the carry-save adder. Then a result is corrected by adding an adjustment of three. This adjustment value is incorporated into the result through the carry-save adder circuit. Thus the circuit produces a valid redundant representation for the subtraction operation A−B.

Abstract translation: 公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，以减去以冗余形式接收的数字，包括从旁路电路接收的数字。 该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。 它还包括向算术电路提供调整输入以增加通过算术电路产生的结果，以产生冗余形式的减法运算来产生有效结果。在本发明的一个优选实施例中使用进位保存加法器结构 执行减法运算AB，其中B是由其有效进位和冗余表示之一表示的数。 为了执行减法运算，B的冗余表示中的每个进位位和每个和位被补码并提供给进位存储加法器。 然后通过添加三个调整来校正结果。 该调整值通过进位保存加法器电路并入结果。 因此，该电路产生用于减法运算A-B的有效冗余表示。