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    PARTITION-FREE MULTI-SOCKET MEMORY SYSTEM ARCHITECTURE
    31.
    发明申请
    PARTITION-FREE MULTI-SOCKET MEMORY SYSTEM ARCHITECTURE 有权
    无分区多点存储器系统架构

    公开(公告)号：US20090248990A1

    公开(公告)日：2009-10-01

    申请号：US12059193

    申请日：2008-03-31

    Applicant: Eric Sprangle

    Inventor： Eric Sprangle

    IPC: G06F12/00 ,  G06F9/30

    CPC classification number: G06T1/20 ,  G06F3/0644 ,  G06F9/30043 ,  G06F9/3867 ,  G06F9/5016

    Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.

    Abstract translation: 增加吞吐量应用程序的内存带宽的技术。 在一个实施例中，特别是对于吞吐量应用而言，可以增加存储器带宽，而不会通过在存储器访问时钟的半周期上的一个或多个存储器存储区域之间流水线页面来增加互连轨迹或引脚数。

    DEVICE, SYSTEM, AND METHOD FOR GATHERING ELEMENTS FROM MEMORY
    32.
    发明申请
    DEVICE, SYSTEM, AND METHOD FOR GATHERING ELEMENTS FROM MEMORY 有权
    用于从记忆中获取元素的装置，系统和方法

    公开(公告)号：US20090172364A1

    公开(公告)日：2009-07-02

    申请号：US11967482

    申请日：2007-12-31

    Applicant: Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Tom Forsyth ,  Michael Abrash

    Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Tom Forsyth ,  Michael Abrash

    IPC: G06F9/315 ,  G06F12/02

    CPC classification number: G06F15/8069 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/345 ,  G06F9/383 ,  G06F12/02 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/6028

    Abstract: A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.

    Abstract translation: 一种用于向第一寄存器中的元素分配值的系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段，第一值可以 指示对应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中的每个数据字段的值，并且对于每个数据 在第一寄存器中具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。 描述和要求保护其他实施例。

    MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS
    33.
    发明申请
    MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS 有权
    有效的高速缓存和非流动数据模式的机制

    公开(公告)号：US20090172291A1

    公开(公告)日：2009-07-02

    申请号：US11967413

    申请日：2007-12-31

    Applicant: Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin

    Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin

    IPC: G06F12/00

    CPC classification number: G06F12/127 ,  G06F12/0862 ,  G06F12/124 ,  G06F2212/6028

    Abstract: A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.

    Abstract translation: 本文描述了用于有效地高速缓存流和非流数据的方法和装置。 诸如编译器的软件识别最后使用的流指令/操作，这些指令/操作是用于访问多个指令或一定时间量的最后指令/操作来访问流数据。 作为执行对最后使用指令/操作的高速缓存线的访问的结果，将高速缓存行更新为不再需要的流数据（SDN）状态。 当控制逻辑要确定要替换的高速缓存行时，修改的最近最少使用（LRU）算法被偏置以首先选择SDN状态行来替换不再需要的流数据。

    Prefetching data in a computer system
    35.
    发明申请
    Prefetching data in a computer system 有权
    在计算机系统中预取数据

    公开(公告)号：US20060117145A1

    公开(公告)日：2006-06-01

    申请号：US11331658

    申请日：2006-01-12

    Applicant: Eric Sprangle ,  Anwar Rohillah

    Inventor： Eric Sprangle ,  Anwar Rohillah

    IPC: G06F12/00

    CPC classification number: G06F12/0897 ,  G06F12/0862

    Abstract: A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.

    Abstract translation: 一种用于检测和过滤预取输入队列中的冗余高速缓存行地址的方法和装置，并且根据用于高速缓存到存储器控制器总线的队列中的检测器条目的数量动态地调整检测器窗口大小。 检测器对应于高速缓存行地址，这可能代表各级高速缓存中的高速缓存未命中。

    Method and apparatus for determining a dynamic random access memory page management implementation
    36.
    发明申请
    Method and apparatus for determining a dynamic random access memory page management implementation 有权

    公开(公告)号：US20060112255A1

    公开(公告)日：2006-05-25

    申请号：US11323598

    申请日：2005-12-30

    Applicant: Eric Sprangle ,  Anwar Rohillah

    Inventor： Eric Sprangle ,  Anwar Rohillah

    IPC: G06F12/02

    CPC classification number: G06F13/1631 ,  G06F12/0215

    Abstract: A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.

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