公开(公告)号：US10355086B2

公开(公告)日：2019-07-16

申请号：US15181843

申请日：2016-06-14

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/84 ,  H01L29/10 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20 ,  H01L29/417 ,  H01L29/78

摘要： A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

公开(公告)号：US20190206868A1

公开(公告)日：2019-07-04

申请号：US16294117

申请日：2019-03-06

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/033 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165 ,  H01L29/10 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L27/0924 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/7849

摘要： A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

公开(公告)号：US10283423B2

公开(公告)日：2019-05-07

申请号：US15292184

申请日：2016-10-13

申请人： International Business Machines Corporation ,  Globalfoundries, Inc.

发明人： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC分类号： H01L21/66 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66

摘要： Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

公开(公告)号：US20180175202A1

公开(公告)日：2018-06-21

申请号：US15890880

申请日：2018-02-07

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/417 ,  H01L21/306 ,  H01L29/66

CPC分类号： H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

公开(公告)号：US09935179B2

公开(公告)日：2018-04-03

申请号：US15472556

申请日：2017-03-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

发明人： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

摘要： A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

公开(公告)号：US09773885B2

公开(公告)日：2017-09-26

申请号：US15471733

申请日：2017-03-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

发明人： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306

CPC分类号： H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US20170033197A1

公开(公告)日：2017-02-02

申请号：US15181843

申请日：2016-06-14

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L21/306 ,  H01L29/08

CPC分类号： H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

摘要翻译： 半导体器件包括在衬底中图案化的鳍; 设置在所述翅片上并基本上垂直于所述翅片的门; 一对外延触点，包括在鳍的上方和栅极的相对侧上的III-V材料; 以及在栅极之间的一对外延触点之间的沟道区，其包括在掺杂III-V材料之间的未掺杂的III-V材料，掺杂的III-V材料包括量为约1e18至约1e20原子/ 并与外延触点接触。

公开(公告)号：US20160372332A1

公开(公告)日：2016-12-22

申请号：US15240554

申请日：2016-08-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc

发明人： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L21/285 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

CPC分类号： H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

公开(公告)号：US20160284822A1

公开(公告)日：2016-09-29

申请号：US15178853

申请日：2016-06-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/08

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

摘要： A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

摘要翻译： 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US20160284599A1

公开(公告)日：2016-09-29

申请号：US15179620

申请日：2016-06-10

申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

发明人： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC分类号： H01L21/8234 ,  H01L21/285 ,  H01L21/84

CPC分类号： H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

摘要翻译： 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地被金属材料填充以形成埋在衬底中的源极（或漏极）触点。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。