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    VERTICALLY STACKED COMPLEMENTARY-FET DEVICE WITH INDEPENDENT GATE CONTROL
    31.
    发明申请
    VERTICALLY STACKED COMPLEMENTARY-FET DEVICE WITH INDEPENDENT GATE CONTROL 审中-公开

    公开(公告)号：US20200035569A1

    公开(公告)日：2020-01-30

    申请号：US16577032

    申请日：2019-09-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet Harischandra Suvarna

    IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/822 ,  H01L27/12 ,  H01L27/092

    Abstract: A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.

    Transistors with H-shaped or U-shaped channels and method for forming the same
    32.
    发明授权
    Transistors with H-shaped or U-shaped channels and method for forming the same 有权

    公开(公告)号：US10381459B2

    公开(公告)日：2019-08-13

    申请号：US15865973

    申请日：2018-01-09

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Julien Frougier ,  Yi Qi ,  Nigel G. Cave ,  Edward J. Nowak ,  Andreas Knorr

    IPC: H01L21/44 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/308 ,  H01L29/161 ,  H01L29/06 ,  H01L29/78

    Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

    Insulated epitaxial structures in nanosheet complementary field effect transistors
    33.
    发明授权
    Insulated epitaxial structures in nanosheet complementary field effect transistors 有权

    公开(公告)号：US10256158B1

    公开(公告)日：2019-04-09

    申请号：US15820477

    申请日：2017-11-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Julien Frougier ,  Ruilong Xie ,  Steven Bentley ,  Puneet H. Suvarna

    IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/167 ,  H01L29/423 ,  H01L27/092 ,  H01L21/822 ,  H01L29/161 ,  H01L21/84

    Abstract: Integrated circuit structures include isolation elements extending into a substrate, and source/drain regions of a first transistor contacting the isolation elements. The isolation elements extend from the substrate to the source/drain regions of the first transistor. Isolation layers contact the source/drain regions of the first transistor, and source/drain regions of a second transistor also contact the isolation layers. Thus, the isolation layers are between the source/drain regions of the first transistor and the source/drain regions of the second transistor. Channel regions of the first transistor contact and extend between the source/drain regions of the first transistor, and channel regions of the second transistor contact and extend between the source/drain regions of the second transistor. A gate conductor surrounds sides of the channel region of the first transistor and the channel region of the second transistor.

    Gate-all-around field effect transistors with air-gap inner spacers and methods
    38.
    发明授权
    Gate-all-around field effect transistors with air-gap inner spacers and methods 有权

    公开(公告)号：US10692991B2

    公开(公告)日：2020-06-23

    申请号：US16123160

    申请日：2018-09-06

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Daniel Chanemougame ,  Julien Frougier ,  Ruilong Xie

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3065

    Abstract: Disclosed are structures including a gate-all-around field effect transistor (GAAFET) with air-gap inner spacers. The GAAFET includes a stack of nanoshapes that extend laterally between source/drain regions, a gate that wraps around a center portion of each nanoshape, and a gate sidewall spacer on external sidewalls of the gate. The GAAFET also includes air-gap inner spacers between the gate and the source/drain regions. Each air-gap inner spacer includes: two vertical sections within the gate sidewall spacer on opposing sides of the stack and adjacent to a source/drain region; and horizontal sections below the nanoshapes and extending laterally between the vertical sections. Also discloses are methods of forming the structures and the method include forming preliminary inner spacers in inner spacer cavities prior to source/drain region formation. After source/drain regions are formed, the preliminary inner spacers are removed and the cavities are sealed off, thereby forming the air-gap inner spacers.

    NANOSHEET FIELD-EFFECT TRANSISTOR WITH SUBSTRATE ISOLATION
    39.
    发明申请
    NANOSHEET FIELD-EFFECT TRANSISTOR WITH SUBSTRATE ISOLATION 审中-公开

    公开(公告)号：US20200152734A1

    公开(公告)日：2020-05-14

    申请号：US16185881

    申请日：2018-11-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie

    IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78

    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A sacrificial layer is epitaxially grown on a bulk semiconductor substrate, a plurality of epitaxial semiconductor layers are epitaxially grown over the sacrificial layer, and the sacrificial layer and the plurality of epitaxial semiconductor layers are patterned to form a fin. A first portion of the first sacrificial layer is removed to form a first cavity arranged between the plurality of epitaxial semiconductor layers and the bulk semiconductor substrate, and a first dielectric material is deposited in the first cavity. A second portion of the first sacrificial layer, which is located adjacent to the first dielectric material in the first cavity, is removed to form a second cavity between the first fin and the bulk semiconductor substrate. A second dielectric material is deposited in the second cavity.

    HYBRID DUAL DAMASCENE STRUCTURES WITH ENLARGED CONTACTS
    40.
    发明申请
    HYBRID DUAL DAMASCENE STRUCTURES WITH ENLARGED CONTACTS 审中-公开

    公开(公告)号：US20200075456A1

    公开(公告)日：2020-03-05

    申请号：US16114600

    申请日：2018-08-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Daniel Chanemougame ,  Julien Frougier ,  Ruilong Xie

    IPC: H01L23/48 ,  H01L21/768 ,  H01L29/08 ,  H01L23/532

    Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A contact structure is formed that includes a first contact arranged over a source/drain region and a second contact arranged over the first contact. A dielectric cap is formed over the second contact. A via is formed that extends in a vertical direction through the dielectric cap to the second contact. An interconnect is formed over the dielectric cap, and is connected by the via with the second contact.

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