公开(公告)号：US08839168B2

公开(公告)日：2014-09-16

申请号：US13746508

申请日：2013-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jongwook Kye ,  Harry J Levinson ,  Jason E Stephens ,  Lei Yuan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.

Abstract translation: 公开了一种用于确定与自对准双重图案（SADP）技术一起使用的通孔外壳规则的设计方法。 块掩模的形状作为选择通孔封套规则的标准。 集成电路设计中不同的块掩模形状可以利用不同的规则，并为通孔外壳提供不同的边缘。 紧密的通孔外壳设计规则可能会减少超出通孔的线的余量，而松动的通孔外壳设计规则可增加超出通孔的线的裕度，从而有利于此。

公开(公告)号：US10147714B2

公开(公告)日：2018-12-04

申请号：US15289401

申请日：2016-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yan Wang ,  Jia Zeng ,  Chenchen Wang ,  Wenhui Wang ,  Lei Yuan ,  Jongwook Kye

IPC: H01L27/02 ,  H01L21/768 ,  G06F17/50

Abstract: At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first power rail is formed in a first direction. A second portion of the first power rail is formed in a second direction in the first location for the two-dimensional portion.

公开(公告)号：US20180218981A1

公开(公告)日：2018-08-02

申请号：US15418001

申请日：2017-01-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Irene Y. L. Lin ,  Lei Yuan ,  Mahbub Rashed

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118 ,  G06F17/50

CPC classification number: H01L23/5286 ,  G06F17/5077 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11887

Abstract: A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.

公开(公告)号：US20170207165A1

公开(公告)日：2017-07-20

申请号：US15473371

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Juhan Kim

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/522 ,  G06F17/50 ,  H01L27/02

CPC classification number: H01L23/5286 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/027 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0886 ,  H01L28/00 ,  Y02P90/265

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device comprising an asymmetrically placed metal formation. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first metal formation is placed asymmetrically about a first cell boundary of the functional cell for providing additional space for routing.

公开(公告)号：US09639650B2

公开(公告)日：2017-05-02

申请号：US14716565

申请日：2015-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim

IPC: G06F17/50 ,  H01L21/00 ,  H01L21/027

CPC classification number: H01L23/5286 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/027 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0886 ,  H01L28/00 ,  Y02P90/265

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device comprising an asymmetrically placed metal formation. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first metal formation is placed asymmetrically about a first cell boundary of the functional cell for providing additional space for routing.

公开(公告)号：US09627389B1

公开(公告)日：2017-04-18

申请号：US15003304

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Lei Yuan ,  Srinivasa Banna

IPC: H01L21/311 ,  H01L27/11 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Methods to utilize efficient processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing mandrels separated from each other across two adjacent bit-cells on an upper surface of a dielectric layer on an upper surface of a silicon (Si) layer; forming first spacers on opposite sides of each mandrel; forming second spacers on exposed sides of the first spacers; removing the mandrels; removing exposed sections of the dielectric layer; removing the first and second spacers; forming fin-spacers on opposite sides of remaining sections of the dielectric layer; removing the remaining sections of the dielectric layer; removing exposed sections of the Si layer; and removing the fin-spacers to reveal Si fins.

公开(公告)号：US09536778B2

公开(公告)日：2017-01-03

申请号：US14679060

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J Levinson

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/532

CPC classification number: H01L21/76802 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257

Abstract: Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Abstract translation: 公开了用于在导线之间产生金属路径的自对准双重图案化工艺。 实施例包括在电介质层上形成硬掩模; 在硬掩模上形成包括多个平行线形元件的图案化模板，其中所述硬掩模在相邻的平行线性元件之间露出; 形成覆盖所述相邻的平行线性元件的一部分和其间的空间的块掩模; 通过所述块掩模蚀刻所述硬掩模的暴露部分和限定多条平行线的所述图案化模板; 去除所述块掩模和所述图案化模板; 在所述硬掩模上形成切割掩模以限定垂直于并连接两个相邻平行线的开口; 通过所述切割掩模蚀刻所述硬掩模并除去切割的掩模; 通过所述硬掩模蚀刻介电层中的凹槽; 去除硬面膜; 并用导电材料填充所述凹部。

公开(公告)号：US20160336183A1

公开(公告)日：2016-11-17

申请号：US14712767

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L21/285 ,  H01L29/78 ,  H01L21/67 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/401 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein for processing a semiconductor wafer using a continuous active area design for manufacturing a finFET device. A first gate structure of a continuous active area design is formed in a first layer of the wafer. A first hard mask layer is deposited. A portion of the first hard mask layer is removed based upon a first trench silicide (TS) pattern and a second TS pattern. A full stripe first trench silicide (TS) structure and a second TS structure are formed. A first TS capping layer is deposited above the first TS structure and a second TS capping. The first TS capping layer is removed and a source/drain contact structure (CA) is formed above the first TS structure in a second layer of the semiconductor wafer. A gate contact structure (CB) is formed above the gate structure in the second layer.

Abstract translation: 本文公开的至少一种方法，装置和系统，用于使用用于制造finFET器件的连续有源区域设计来处理半导体晶片。 连续有源区域设计的第一栅极结构形成在晶片的第一层中。 沉积第一个硬掩模层。 基于第一沟槽硅化物（TS）图案和第二TS图案去除第一硬掩模层的一部分。 形成全条纹第一沟槽硅化物（TS）结构和第二TS结构。 第一TS封装层沉积在第一TS结构上方，并且第二TS覆盖层。 去除第一TS封盖层，并且在半导体晶片的第二层中的第一TS结构之上形成源极/漏极接触结构（CA）。 栅极接触结构（CB）形成在第二层中的栅极结构的上方。

公开(公告)号：US20160335389A1

公开(公告)日：2016-11-17

申请号：US14712830

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Yan Wang ,  Chenchen Wang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value.

Abstract translation: 所公开的至少一种方法，装置和系统涉及用于集成电路装置的电路布局。 接收集成电路装置的设计。 该设计包括功能单元。 提供了与功能单元的边界相对应的一组路线轨迹的第一移位值的第一替代功能单元。 第一替代功能单元包括移动了第一值的量的至少一个销。 确定路由路径组的移位量是否对应于第一值。 响应于确定路由路径集合的偏移量对应于第一值，功能单元被第一替代功能单元替换。

公开(公告)号：US20150331988A1

公开(公告)日：2015-11-19

申请号：US14809698

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。