公开(公告)号：US10103224B2

公开(公告)日：2018-10-16

申请号：US15457384

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Steffen Sichler

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/08 ,  H01L23/535

Abstract: A semiconductor structure includes a trench isolation structure and a trench capping layer positioned over the trench isolation structure, wherein the trench isolation layer includes a first electrically insulating material and the trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The semiconductor structure also includes a gate structure having a gate insulation layer and a gate electrode positioned over the gate insulation layer, wherein the gate insulation layer includes a high-k material and the gate structure includes a first portion that is positioned over the trench capping layer. A sidewall spacer is positioned adjacent to the gate structure, wherein a portion of the sidewall spacer is positioned on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

公开(公告)号：US09923076B2

公开(公告)日：2018-03-20

申请号：US15185593

申请日：2016-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith

IPC: H01L21/302 ,  H01L29/51 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/51 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6656 ,  H01L29/786

Abstract: A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including forming a multilayer stack for an HKMG gate on a substrate, the multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon, forming a patterned hard mask above the gate electrode layer, etching partially into the gate electrode layer through the patterned hard mask to define multiple partially etched gate stacks and a partially etching gate electrode layer, forming a conformal protective layer wrapping over the partially etched gate electrode layer and the patterned hard mask, and etching through a remainder of the partially etched gate electrode layer with the conformal protective layer wrapped over the partially etched gate stacks and the patterned hard mask, as well as an HKMG transistor resulting therefrom.

公开(公告)号：US20170345914A1

公开(公告)日：2017-11-30

申请号：US15648889

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/308 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/7831

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

公开(公告)号：US20170271220A1

公开(公告)日：2017-09-21

申请号：US15075378

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan

IPC: H01L21/66 ,  H01L29/423 ,  H01L27/12 ,  H01L21/84 ,  H01L27/11 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L22/30 ,  H01L21/30604 ,  H01L21/823456 ,  H01L21/84 ,  H01L22/12 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/4236

Abstract: In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor substrate, forming a plurality of trenches in the test region, the trenches of the plurality of trenches having at least one of a varying width, a varying length, and a varying bridge between adjacent trenches, determining depth values of the trenches, and evaluating the risk of defects of gate electrodes to be formed on the basis of the depth values.

公开(公告)号：US09685336B1

公开(公告)日：2017-06-20

申请号：US15055954

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Elliot John Smith

IPC: H01L21/66 ,  H01L21/28 ,  H01L21/033

CPC classification number: H01L21/28123 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/26

Abstract: A method of monitoring critical dimensions of gate electrode structures is provided including providing a substrate, forming a gate electrode pattern on the substrate comprising forming gate electrode lines parallel to each other, forming a mask layer on the gate electrode pattern and forming openings in the mask layer in a crosswise direction with respect to the direction of the parallel gate electrode lines, thereby exposing portions of the gate electrode pattern, etching exposed portions of the gate electrode pattern through the mask layer openings, thereby obtaining a negative image of the mask layer openings, removing remaining portions of the mask layer, and monitoring dimensions of the mask layer openings.

公开(公告)号：US20150050812A1

公开(公告)日：2015-02-19

申请号：US13965483

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith

IPC: H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/32862 ,  H01J2237/334 ,  H01L21/67028

Abstract: A method for cleaning a processing chamber, for example, a strip chamber, configured for processing a wafer is provided which includes the steps of introducing an oxygen-containing gas into the processing chamber, generating an oxygen plasma from the oxygen-containing gas in the processing chamber, establishing a pressure of the oxygen plasma in the processing chamber of at least 1 Torr and maintaining the pressure of at least 1 Torr for at least 40 seconds. A system is also provided including a strip chamber for receiving and stripping the wafer and including a gas inlet and plasma generator means, as well as a controller configured for performing, when no wafer is present in the strip chamber, controlling inflow of an oxygen-containing gas into the processing chamber through the gas inlet and controlling the plasma generator means to generate an oxygen plasma.

Abstract translation: 提供了一种用于清洁处理室的方法，例如，用于处理晶片的条形室，其包括以下步骤：将含氧气体引入到处理室中，从而在含氧气体中产生氧等离子体 在处理室中建立至少1托的氧等离子体的压力，并将至少1乇的压力保持至少40秒。 还提供了一种系统，其包括用于接收和剥离晶片的带室，并且包括气体入口和等离子体发生器装置，以及控制器，其被配置为当在带室中没有晶片时，控制氧气 - 通过气体入口将气体进入处理室，并控制等离子体发生器装置以产生氧等离子体。

公开(公告)号：US10811433B2

公开(公告)日：2020-10-20

申请号：US16446906

申请日：2019-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan ,  Nilesh Kenkare

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/8238

Abstract: One illustrative device disclosed herein is formed on an SOI substrate. The transistor device includes a first channel region formed in a semiconductor bulk substrate of the SOI substrate and a first gate insulation layer formed above the first channel region. In one embodiment, the first gate insulation layer includes a part of the buried insulation layer of the SOI substrate and an oxidized part of the semiconductor layer of the SOI substrate.

公开(公告)号：US20200083223A1

公开(公告)日：2020-03-12

申请号：US16129221

申请日：2018-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming-Cheng Chang ,  Nigel Chan ,  Elliot John Smith

IPC: H01L27/092 ,  H03K19/0948 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/762

Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

公开(公告)号：US20190312041A1

公开(公告)日：2019-10-10

申请号：US15944885

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Gunter Grasshoff ,  Carsten Peters

IPC: H01L27/11

Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.

公开(公告)号：US20190312038A1

公开(公告)日：2019-10-10

申请号：US15948016

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nigel Chan ,  Elliot John Smith ,  Ming-Cheng Chang

IPC: H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092

Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which a contact element at the source side of a pull-down transistor in a RAM cell may connect to the back gate region in a fully depleted SOI transistor architecture. In this manner, the complexity of at least some metallization layers may be reduced, thereby providing the potential of reducing parasitic bit line capacitance. Furthermore, in some illustrative embodiments, the contact regime for connecting the back gate region to a reference potential may be omitted, thereby reducing overall floor space of respective designs.