公开(公告)号：US20190355615A1

公开(公告)日：2019-11-21

申请号：US16525601

申请日：2019-07-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jiehui Shu ,  Garo Jacques Derderian ,  Hui Zang ,  John Zhang ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

公开(公告)号：US10460986B2

公开(公告)日：2019-10-29

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Chih-Chiang Chang ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Mitchell Rutkowski ,  Haigou Huang ,  Huy Cao

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US10325819B1

公开(公告)日：2019-06-18

申请号：US15920303

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3105

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.

公开(公告)号：US10256089B2

公开(公告)日：2019-04-09

申请号：US15626732

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Haigou Huang ,  Jinsheng Gao ,  Tai Fong Chao

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28

Abstract: Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate structure. The sacrificial contact extends vertically to a source/drain region. A section of the sacrificial contact is removed to form a cut opening extending vertically to the source/drain region. A first dielectric layer is deposited in the cut opening, and is then partially removed to open a space in the cut opening that is arranged vertically above the first dielectric layer. A second dielectric layer is deposited that fills the space in the cut opening and forms a cap on the first dielectric layer. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20180366324A1

公开(公告)日：2018-12-20

申请号：US15626732

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Haigou Huang ,  Jinsheng Gao ,  Tai Fong Chao

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L21/02378 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/28255 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76888 ,  H01L29/41775

Abstract: Interconnect structures and methods of forming an interconnect structure. A sacrificial contact is arranged between a first gate structure and a second gate structure. The sacrificial contact extends vertically to a source/drain region. A section of the sacrificial contact is removed to form a cut opening extending vertically to the source/drain region. A first dielectric layer is deposited in the cut opening, and is then partially removed to open a space in the cut opening that is arranged vertically above the first dielectric layer. A second dielectric layer is deposited that fills the space in the cut opening and forms a cap on the first dielectric layer. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20180248046A1

公开(公告)日：2018-08-30

申请号：US15445392

申请日：2017-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Jiehui Shu

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78684

Abstract: A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure.

公开(公告)号：US09991363B1

公开(公告)日：2018-06-05

申请号：US15657594

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinsheng Gao ,  Haifeng Sheng ,  Jinping Liu ,  Huy Cao ,  Hui Zang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32105 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437

Abstract: A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During subsequent processing, the polysilicon layer is adapted to oxidize and form an oxide layer. The oxidation of the polysilicon layer effectively shields the underlying nitride contact etch stop layer from oxidation, which protects the mechanical integrity of the nitride layer.

公开(公告)号：US09935012B1

公开(公告)日：2018-04-03

申请号：US15361824

申请日：2016-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Haigou Huang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/027 ,  H01L21/308 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823412 ,  H01L29/16 ,  H01L29/66795

Abstract: Disclosed are methods of forming different shapes in different regions of a specific layer. In the methods, a first mask layer and an etch process are used to form first shapes in a first region. Subsequently, a second mask layer and additional etch process(es) are used to form second shapes in a second region. However, before the second shapes are formed, a sacrificial layer of a degradable material is deposited onto the first mask layer and within openings in the specific layer surrounding the first shapes, thereby protecting the first shapes during formation of the second shapes. After the second shapes are formed, the material of the sacrificial layer is degraded (e.g., oxidized, volatilized, burned-off, etc.) so as to selectively remove that material from surfaces of the first mask layer and the specific layer without impacting the profiles of either the first shapes or the second shapes.

公开(公告)号：US09916982B1

公开(公告)日：2018-03-13

申请号：US15383461

申请日：2016-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Haigou Huang ,  John Zhang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/283

CPC classification number: H01L21/823437 ,  H01L21/283 ,  H01L21/8234 ,  H01L21/823468 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78

Abstract: Structures for use in a replacement gate process involving a field-effect transistor and methods for forming such structures. A first dielectric layer is formed adjacent to a dummy gate structure, and a second dielectric layer is formed on the first dielectric layer. After the second dielectric layer is formed, a portion of the dummy gate structure is removed with an etching process to cut the dummy gate structure into disconnected segments. The second dielectric layer caps the first dielectric layer when the portion of the dummy gate structure is removed. The second dielectric layer has a higher etch rate selectivity than the first dielectric layer to the etching process.

公开(公告)号：US20170338226A1

公开(公告)日：2017-11-23

申请号：US15628984

申请日：2017-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Taifong Chao

IPC: H01L27/088 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66803 ,  H01L29/7856

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, an integrated circuit (IC) structure includes: a substrate; a set of fin structures overlying the substrate, the set of fin structures including a substrate base and a silicide layer over the substrate base; an oxide layer located between adjacent fins in the set of fin structures; and a nitride layer over the set of fin structures, wherein a height of the nitride layer is substantially uniform across the set of fin structures.