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    LDMOS WITH IMPROVED BREAKDOWN VOLTAGE
    31.
    发明申请
    LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 审中-公开
    LDMOS具有改进的断电电压

    公开(公告)号：US20150325697A1

    公开(公告)日：2015-11-12

    申请号：US14713819

    申请日：2015-05-15

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Jae Gon LEE ,  Chung Foong TAN ,  Elgin QUEK

    IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06

    CPC classification number: H01L29/7816 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

    Abstract: An LDMOS is formed with a second gate stack over n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include a device including a substrate; a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well; a source in the first well and a drain in the second well; a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well; a first gate stack on a portion of the first well; a second gate stack on a portion of the second well, the first and second gate stacks having a common gate electrode.

    Abstract translation: LDMOS由n-漂移区上的第二栅极堆叠形成，具有与栅极堆叠相同的公共栅电极，并具有比栅叠层更高的功函数。 实施例包括：包括基板的装置; 在衬底中的第一阱和第二阱，所述第一阱掺杂有第一导电类型的掺杂剂，所述第二阱掺杂有第二导电型掺杂剂，所述第二阱围绕所述第一阱; 第一口井的源头和第二口井的排水沟; 所述第一阱中的所述第一导电类型掺杂剂的掺杂区域，所述掺杂区域用作与所述第一阱的体接触; 在第一井的一部分上的第一栅极堆叠; 在第二阱的一部分上的第二栅极堆叠，第一和第二栅极堆叠具有公共栅电极。

    SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE
    32.
    发明申请
    SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE 审中-公开
    分屏门闪存显示减少干扰

    公开(公告)号：US20150255471A1

    公开(公告)日：2015-09-10

    申请号：US14716951

    申请日：2015-05-20

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Shyue Seng TAN ,  Elgin QUEK

    IPC: H01L27/115 ,  H01L29/51

    CPC classification number: H01L27/11517 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/513

    Abstract: A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

    Abstract translation: 分离栅极存储单元由在栅极和存储器栅极堆叠之间的包含高k材料的介电隔离器制造。 实施例包括具有包含低k和高k层的电介质间隔物的存储单元。 其他实施例包括在字门和存储器栅叠层之间具有气隙的存储单元。

    TUNNELING TRANSISTOR
    34.
    发明申请
    TUNNELING TRANSISTOR 有权
    隧道晶体管

    公开(公告)号：US20140175381A1

    公开(公告)日：2014-06-26

    申请号：US13727547

    申请日：2012-12-26

    Applicant: NATIONAL UNIVERSITY OF SINGAPORE ,  GLOBALFOUNDRIES SINGAPORE PTE. LTD.

    Inventor： Kian Hui GOH ,  Eng Huat TOH ,  Yee Chia YEO

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7851 ,  H01L29/0673 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/785

    Abstract: Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness TCH.

    Abstract translation: 提出了用于形成装置的装置和方法。 该器件包括衬底和布置在衬底上的鳍型晶体管。 晶体管包括用作晶体管本体的鳍结构。 翅片结构包括第一和第二端部区域以及第一和第二端部区域之间的中间区域。 源极区域设置在第一端部区域上，漏极区域设置在第二端部区域中，栅极设置在鳍状结构的中间区域上。 该器件包括邻近源极区设置的沟道区和栅极的栅极电介质。 源极隧道结与栅极对准，具有受控的沟道厚度TCH。

    DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS
    35.
    发明申请
    DEEP DEPLETED CHANNEL MOSFET WITH MINIMIZED DOPANT FLUCTUATION AND DIFFUSION LEVELS 有权
    具有最小化絮凝物渗透和扩散水平的深层通道MOSFET

    公开(公告)号：US20140159168A1

    公开(公告)日：2014-06-12

    申请号：US14177983

    申请日：2014-02-11

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Shyue Seng TAN

    IPC: H01L29/78

    CPC classification number: H01L29/78 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834

    Abstract: CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity.

    Abstract translation: CMOS器件制造具有最小化掺杂剂波动和扩散的沟道层。 实施例包括在一对衬垫之间在衬底上形成一个虚拟栅极，在衬底中形成由接地平面层分隔开的源极和漏极，从衬底去除虚拟栅极，在该对间隔物之间​​形成空腔 在去除所述虚拟栅极之后，在所述衬底上形成沟道层，在所述沟道层和所述腔的侧表面上形成高k层，并且在所述空腔中形成替换栅极。

    VERTICAL NANOWIRE BASED HETERO-STRUCTURE SPLIT GATE MEMORY
    36.
    发明申请
    VERTICAL NANOWIRE BASED HETERO-STRUCTURE SPLIT GATE MEMORY 有权
    基于NANOWIRE的立体异构结构分离器存储器

    公开(公告)号：US20140159114A1

    公开(公告)日：2014-06-12

    申请号：US13707617

    申请日：2012-12-07

    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

    Inventor： Ping ZHENG ,  Eng Huat TOH ,  Yuan SUN

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/78 ,  G11C16/00 ,  H01L27/11582 ,  H01L29/66477 ,  H01L29/66833 ,  H01L29/7926

    Abstract: A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell.

    Abstract translation: 公开了一种存储器单元。 存储单元包括设置在基板上的垂直基板。 垂直底座包括顶部和底部端子之间的第一和第二通道。 存储单元还包括围绕第一通道的第一栅极和围绕第二通道的第二栅极。 第一和第二栅极形成存储器单元的全栅三极管。

    SENSOR DEVICES
    39.
    发明申请
    SENSOR DEVICES 有权

    公开(公告)号：US20220205948A1

    公开(公告)日：2022-06-30

    申请号：US17699219

    申请日：2022-03-21

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lanxiang WANG ,  Bin LIU ,  Eng Huat TOH ,  Shyue Seng TAN ,  Kiok Boone Elgin QUEK

    IPC: G01N27/414 ,  H01L29/16 ,  H01L29/04

    Abstract: According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.

    MEMORY STRUCTURES AND METHODS OF FORMING MEMORY STRUCTURES
    40.
    发明申请
    MEMORY STRUCTURES AND METHODS OF FORMING MEMORY STRUCTURES 有权

    公开(公告)号：US20220139929A1

    公开(公告)日：2022-05-05

    申请号：US17087683

    申请日：2020-11-03

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Xinshu CAI ,  Yongshun SUN ,  Lanxiang WANG ,  Eng Huat TOH ,  Shyue Seng TAN

    IPC: H01L27/1156 ,  H01L29/06

    Abstract: A memory structure may be provided, including a substrate, and a first well region, a second well region, and a third well region arranged within the substrate, where the first well region and the third well region may have a first conductivity type, and the second well region may have a second conductivity type different from the first conductivity type, and where the second well region may be arranged laterally between the first well region and the third well region. The memory structure may further include a first gate structure and a second gate structure arranged over the second well region. The first gate structure may extend over the third well region and the second gate structure may extend over the first well region.

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