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    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position
    32.
    发明申请
    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效
    网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置

    公开(公告)号：US20060101172A1

    公开(公告)日：2006-05-11

    申请号：US11320277

    申请日：2005-12-27

    申请人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： G06F5/00

    CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

    摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

    摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

    Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus
    33.
    发明授权
    Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus 失效
    用于实现点对点总线的多个可配置子总线的方法和装置

    公开(公告)号：US06996650B2

    公开(公告)日：2006-02-07

    申请号：US10147682

    申请日：2002-05-16

    申请人： Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

    发明人： Jean Calvignac ,  Marco Heddes ,  Kerry Christopher Imming ,  Christopher Jon Johnson ,  Joseph Franklin Logan ,  Tolga Ozguner

    IPC分类号： G06F13/42 ,  G06F13/14 ,  G06F13/40

    CPC分类号： G06F13/4273 ,  G06F13/4059

    摘要： A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

    摘要翻译： 提供了一种用于实现点对点总线的多个可配置子总线的方法和装置。 多个总线互连中的每一个包括连接到点对点总线的发送接口和接收接口。 每个发送接口包括耦合在缓冲器和点到点总线之间的发送缓冲器和串行器。 发送缓冲区提供发送源和串行器之间的异步接口。 串行器以第一频率从发送缓冲器接收数据和控制信号，并以更高的第二频率在点对点总线上发送数据和控制信号。 发射导向逻辑耦合在多个总线互连的发射源和每个发射缓冲器之间。 发射导向逻辑基于所选择的总线配置将数据和控制信号从发射源引导到每个所选发射缓冲器中的一个。

    Configurable gigabits switch adapter
    35.
    发明授权
    Configurable gigabits switch adapter 失效
    可配置千兆开关适配器

    公开(公告)号：US5311509A

    公开(公告)日：1994-05-10

    申请号：US832127

    申请日：1992-02-06

    申请人： Marco Heddes ,  Ronald Luijten

    发明人： Marco Heddes ,  Ronald Luijten

    IPC分类号： H04L29/06 ,  H04L12/56

    CPC分类号： H04L49/3081 ,  H04L49/20 ,  H04L49/3063 ,  H04L2012/5653 ,  H04L49/30 ,  H04L49/55

    摘要： The present invention relates to a data transmission system and concerns a method for transforming user frames into fixed length cells, e.g. ATM (Asynchronous Transfer Mode), such that the fixed length cells can be transported through a cell handling switch fabric (11). A hardware implementation of this method consists of two parts, a transmitter (12.1) and a receiver (13.1), both being part of a switching subsystem (10) comprising a switch fabric (11). The transmitter (12.1) buffers user data and segments them into fixed length cells to be transported through said switch (11). The receiver part (13.1) reassembles user data on reception of these cells.

    摘要翻译： 本发明涉及一种数据传输系统，涉及将用户帧转换为固定长度小区的方法，例如， ATM（异步传输模式），使得固定长度的小区可以通过小区处理交换结构（11）传输。 该方法的硬件实现包括两个部分：发射机（12.1）和接收机（13.1），它们都是包括交换结构（11）的交换子系统（10）的一部分。 发射机（12.1）缓冲用户数据并将它们分段成固定长度的小区，以便通过所述交换机（11）传输。 接收器部分（13.1）在接收到这些单元时重新组合用户数据。

    System-On-A-Chip Employing A Network Of Nodes That Utilize Logical Channels And Logical Mux Channels For Communicating Messages Therebetween
    36.
    发明申请
    System-On-A-Chip Employing A Network Of Nodes That Utilize Logical Channels And Logical Mux Channels For Communicating Messages Therebetween 审中-公开
    采用使用逻辑通道和逻辑多路复用器通道的节点网络的片上系统在其间通信消息

    公开(公告)号：US20100162265A1

    公开(公告)日：2010-06-24

    申请号：US12342692

    申请日：2008-12-23

    申请人： Marco Heddes

    发明人： Marco Heddes

    IPC分类号： G06F9/46

    CPC分类号： G06F9/542 ,  G06F15/7825 ,  H04L47/10

    摘要： An integrated circuit with an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. A set of logical channels are associated with a logical mux channel. The nodes are adapted to carry out operations utilizing a given logical mux channel associated therewith in order to identify a logical channel that is associated with the given logical mux channel and that has a predetermined ready state. In the preferred embodiment, the operations are invoked by a calling thread that is blocked in the event that no logical channel associated with the given logical mux channel has a predetermined ready state. The calling thread is then reactivated in the event that at least one logical channel associated with the given logical mux channel transitions to the predetermined ready state. Preferably, the nodes include a recirculation queue and logic that stores event messages in the recirculation queue. Each given event message provides an indication that an identified logical channel associated with an identified logical mux channel has transitioned to the predetermined ready state. The logic processes the recirculation queue to reactivate calling threads in accordance with the event messages stored therein. The operations temporarily remove the identified logical channel from the given logical mux channel such that the identified local channel behaves like an independent logic channel. The operations that identify the logical channel associated with the given logical mux channel are fair between all logical channels that are associated with the given logical mux channel.

    摘要翻译： 具有通过片上通信网络链接的节点阵列的集成电路。 使用表示相关节点处的硬件资源的逻辑信道在节点之间传送消息。 给定的逻辑信道与接收机节点和发射机节点相关联。 一组逻辑信道与逻辑多路复用器通道相关联。 节点适于使用与其相关联的给定逻辑多路复用信道来执行操作，以便识别与给定逻辑多路复用器通道相关联且具有预定就绪状态的逻辑信道。 在优选实施例中，在没有与给定逻辑多路复用器通道相关联的逻辑信道具有预定就绪状态的情况下，被调用线程调用该操作。 在与给定逻辑多路复用器通道相关联的至少一个逻辑信道转换到预定就绪状态的情况下，呼叫线程被重新激活。 优选地，节点包括在循环队列中存储事件消息的再循环队列和逻辑。 每个给定的事件消息提供与所识别的逻辑多路复用器信道相关联的所识别的逻辑信道已经转变到预定就绪状态的指示。 逻辑根据存储在其中的事件消息来处理再循环队列重新激活呼叫线程。 操作从给定的逻辑多路复用通道临时移除所识别的逻辑信道，使得所识别的本地信道的行为像独立的逻辑信道。 识别与给定逻辑多路复用器通道相关联的逻辑通道的操作在与给定逻辑多路复用器通道相关联的所有逻辑通道之间是公平的。

    PRIORITY BASED BANDWIDTH ALLOCATION WITHIN REAL-TIME AND NON-REAL TIME TRAFFIC STREAMS
    37.
    发明申请
    PRIORITY BASED BANDWIDTH ALLOCATION WITHIN REAL-TIME AND NON-REAL TIME TRAFFIC STREAMS 有权
    在实时和非实时交通流中基于优先级的带宽分配

    公开(公告)号：US20070081456A1

    公开(公告)日：2007-04-12

    申请号：US11608295

    申请日：2006-12-08

    申请人： Brahmanand Gorti ,  Marco Heddes ,  Clark Jeffries ,  Andreas Kind ,  Michael Siegel

    发明人： Brahmanand Gorti ,  Marco Heddes ,  Clark Jeffries ,  Andreas Kind ,  Michael Siegel

    IPC分类号： H04L12/26 ,  H04L12/56

    CPC分类号： H04L47/6215 ,  H04L47/10 ,  H04L47/2416 ,  H04L47/2433 ,  H04L47/30 ,  H04L47/32 ,  H04L47/50 ,  H04L47/52 ,  H04L47/56

    摘要： A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.

    摘要翻译： 一种用于在分组交换网络中传送分组的方法和系统。 可以基于处理它们的紧急性来优先考虑由分组处理器接收的分组。 紧急处理的数据包可以称为实时数据包。 不紧急处理的数据包可能被称为非实时数据包。 实时数据包的优先级要高于非实时数据包。 可以根据其值优先级，该值优先级的最小和最大速率以及当前实时队列拥塞条件，将实时分组丢弃或传输到实时队列中。 可以基于其值优先级，该值优先级的最小和最大速率以及当前的实时和非实时队列拥塞将非实时分组丢弃或发送到非实时队列 条件。

    LINKING FRAME DATA BY INSERTING QUALIFIERS IN CONTROL BLOCKS
    38.
    发明申请
    LINKING FRAME DATA BY INSERTING QUALIFIERS IN CONTROL BLOCKS 审中-公开
    通过在控制块中插入合格者来连接框架数据

    公开(公告)号：US20070002172A1

    公开(公告)日：2007-01-04

    申请号：US11469390

    申请日：2006-08-31

    申请人： Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： H04N11/00

    CPC分类号： H04L49/3081 ,  G06F13/4243 ,  H04L2012/5681

    摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.

    摘要翻译： 一种通过在控制块中插入限定符来减少存储器访问的方法和系统。 在一个实施例中，系统包括被配置为处理数据帧的处理器。 处理器可以包括多个缓冲器，其被配置为存储数据帧，其中每个数据帧可以与帧控制块相关联。 与数据帧相关联的每个帧控制块可以与一个或多个缓冲器控制块相关联。 每个控制块，例如帧控制块，缓冲器控制块，可以包括包含与当前控制块无关的信息的一个或多个限定符字段。 相反，限定符可以包括与另一个控制块有关的信息。 队列中的最后帧控制块以及与帧控制块相关联的最后一个缓冲器控制块可以包括没有信息的字段，从而减少对这些字段中的访问信息的存储器访问。