公开(公告)号：US20160203835A1

公开(公告)日：2016-07-14

申请号：US15078594

申请日：2016-03-23

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yinyin Lin ,  Yarong Fu ,  Kai Yang ,  Wei Yang ,  Yuangang Wang ,  Junfeng Zhao

IPC: G11B5/09

CPC classification number: G11B5/09 ,  G11B5/02 ,  G11B2005/0002 ,  G11C11/02 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  G11C19/0841

Abstract: An information storage apparatus includes a magnetic track, a writer, and a reader, where the magnetic track includes a number of magnetic domains. Each magnetic domain is divided into at least two magnetic regions, and the writer is disposed on the magnetic track, and configured to write information to the at least two magnetic regions of each magnetic domain. The reader, disposed on the magnetic track, is configured to read the written information from the at least two magnetic regions. Therefore, multiple pieces of valid information are written to one magnetic domain of the magnetic track, thereby increasing storage density of the magnetic track, and expanding a storage capacity of the storage apparatus.

Abstract translation: 信息存储装置包括磁道，写入器和读取器，其中磁道包括多个磁畴。 每个磁畴被分成至少两个磁性区域，并且写入器设置在磁道上，并被配置为将信息写入每个磁畴的至少两个磁性区域。 设置在磁道上的读取器被配置为从至少两个磁性区域读取写入的信息。 因此，将多条有效信息写入磁道的一个磁畴，从而增加磁道的存储密度，并扩大存储装置的存储容量。

公开(公告)号：US20130103975A1

公开(公告)日：2013-04-25

申请号：US13712588

申请日：2012-12-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Haibo Tan ,  Zhenguo Wang ,  Baifeng Yu ,  Ping Huang ,  Junfeng Zhao

IPC: G06F11/20

CPC classification number: G06F11/202 ,  G06F11/2002 ,  G06F11/2017 ,  H04L43/0882

Abstract: Embodiments of the present invention disclose a method for switching an NC link, a processor system, and a node, where the processor system includes more than two nodes capable of communicating with each other, each node includes a node controller NC chip, a host bus adapter HBA apparatus, and at least one CPU, the NC chip is connected to each CPU in a node where the NC chip is located, and the HBA apparatus is connected to each CPU in a node where the HBA apparatus is located; an NC link borne by the NC chip is corresponding to an HBA link borne by the HBA apparatus. By using an HBA apparatus to deploy a redundant link, the cost of deploying the redundant link is reduced effectively under a premise of ensuring the reliability of the processor system.

Abstract translation: 本发明的实施例公开了一种用于切换NC链路，处理器系统和节点的方法，其中处理器系统包括能够彼此通信的多于两个的节点，每个节点包括节点控制器NC芯片，主机总线 适配器HBA装置和至少一个CPU，NC芯片连接到NC芯片所在的节点中的每个CPU，并且HBA装置连接到HBA装置所在的节点中的每个CPU; 由NC芯片承载的NC连接对应于由HBA设备承载的HBA链路。 通过使用HBA设备来部署冗余链路，在确保处理器系统的可靠性的前提下，有效地降低部署冗余链路的成本。

公开(公告)号：US12169432B2

公开(公告)日：2024-12-17

申请号：US17955695

申请日：2022-09-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Liang Shi ,  Xiaolong Shen ,  Weilan Wang ,  Junfeng Zhao ,  Fangmin Lu ,  Xin Yan

IPC: G06F1/00 ,  G06F1/3296 ,  G06F9/4401

Abstract: A device suspension method and a computing device are provided. In the method, before a device enters a suspended state, memory space occupied by a background process that is unrelated to a foreground process is released. In this way, the background process unrelated to the foreground process is not saved in a memory of the device. In other words, it reduces data stored in the memory when the device is suspended. Therefore, when the device needs to be woken up, only a relatively small amount of data needs to be read from the memory, and a working state can be rapidly restored. This can reduce a delay of reading data from the memory when the device is woken up, thereby accelerating a wakeup speed of the device. In addition, the data is stored in the memory when the device is suspended.

公开(公告)号：US11656763B2

公开(公告)日：2023-05-23

申请号：US17306494

申请日：2021-05-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jun Xu ,  Junfeng Zhao ,  Yuangang Wang

IPC: G06F3/06 ,  G06F16/13

CPC classification number: G06F3/0607 ,  G06F3/067 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0652 ,  G06F16/13

Abstract: A file management method, a distributed storage system, and a management node are disclosed. In the distributed storage system, after receiving a file creation request sent by a host for requesting to create a file in a distributed storage system, a management node allocates, to the file, first virtual space from global virtual address space of the distributed storage system, where local virtual address space of each storage node in the distributed storage system is corresponding to a part of the global virtual address space. Then, the management node records metadata of the file, where the metadata of the file includes information about the first virtual space, and the information about the first virtual space is used to point to local virtual address space of a storage node that is used to store the file. Further, the management node sends, the information about the first virtual space to the host.

公开(公告)号：US10223273B2

公开(公告)日：2019-03-05

申请号：US15638582

申请日：2017-06-30

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  Fudan University

Inventor： RenHua Yang ,  Junfeng Zhao ,  Wei Yang ,  Yuangang Wang ,  Yinyin Lin

IPC: G06F12/02 ,  G06F12/0868 ,  G06F13/28 ,  G06F11/14 ,  G06F12/0802 ,  G06F12/109 ,  G11C11/406

Abstract: A memory access method, a storage-class memory, and a computer system are provided. The computer system includes a memory controller and a hybrid memory, and the hybrid memory includes a dynamic random access memory (DRAM) and a storage-class memory (SCM). The memory controller sends a first access instruction to the DRAM and the SCM. When determining that a first memory cell set that is of the DRAM and to which a first address in the received first access instruction points includes a memory cell whose retention time is shorter than a refresh cycle of the DRAM, the SCM may obtain a second address having a mapping relationship with the first address. Further, the SCM converts, according to the second address, the first access instruction into a second access instruction for accessing the SCM, to implement access to the SCM.

公开(公告)号：US10083749B2

公开(公告)日：2018-09-25

申请号：US15412795

申请日：2017-01-23

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhen Li ,  Qiang He ,  Xiangshui Miao ,  Ronggang Xu ,  Junfeng Zhao ,  Zhulin Wei

IPC: G11C11/56 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C7/02 ,  G11C11/5678 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/0092

Abstract: A data storage method applying to a phase change memory and the phase change memory are provided. After obtaining to-be-stored data, the phase change memory (PCM) generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal includes at least two contiguous pulses. Intervals between the at least two contiguous pulses are the same. The intervals between the at least two contiguous pulses have a value determined according to the to-be-stored data. The PCM applies the erase pulse signal to a storage unit of the PCM to enable the storage unit to change to a crystalline state. Further, the write pulse signal is applied to the storage unit to enable the storage unit to change to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

公开(公告)号：US09824739B2

公开(公告)日：2017-11-21

申请号：US15406209

申请日：2017-01-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Kai Yang ,  Junfeng Zhao ,  Yuangang Wang ,  Wei Yang ,  Yinyin Lin ,  Yarong Fu

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607 ,  G11C19/0808 ,  G11C19/0841 ,  G11C19/0866

Abstract: A magnetic storage apparatus is disclosed, and is configured to access data. The magnetic storage apparatus includes a magnetic storage track, a first write apparatus, a second write apparatus, and a drive apparatus. The first write apparatus and the second write apparatus are located at different positions on the magnetic storage track. The first write apparatus is configured to write first data “0” or second data “1”. The second write apparatus is configured to write third data “2” and fourth data “3”.

公开(公告)号：US09800334B2

公开(公告)日：2017-10-24

申请号：US15070212

申请日：2016-03-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiaowen Dong ,  Junfeng Zhao ,  Wei Yang

IPC: H04B10/116 ,  G01S11/12

CPC classification number: H04B10/116 ,  G01S11/12

Abstract: A positioning method based on a visible light source, a mobile terminal, and a controller. The method includes acquiring, by a visible light source controller, geographical position attribute information of a position at which a visible light source array is located, determining, by the visible light source controller according to a preset correspondence between geographical position attribute information of a position at which a visible light source array is located and a visible light source array pattern, a visible light source array pattern corresponding to the acquired geographical position attribute information, and controlling, by the visible light source controller according to the determined visible light source array pattern, the luminance state of each visible light source included in the visible light source array. Hence the method reduces the complexity of a positioning process.

公开(公告)号：US09767900B2

公开(公告)日：2017-09-19

申请号：US15266367

申请日：2016-09-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiangshui Miao ,  Yi Li ,  Yaxiong Zhou ,  Ronggang Xu ,  Junfeng Zhao ,  Zhulin Wei

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463

Abstract: A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter. The logical operation array is set for performing logical operation and enable to storage output level signal in one resistive random access memory after the logical operation

公开(公告)号：US20170263295A1

公开(公告)日：2017-09-14

申请号：US15607360

申请日：2017-05-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Wei Yang ,  Junfeng Zhao

IPC: G11C8/16 ,  G06F3/06

CPC classification number: G11C8/16 ,  G06F3/0659 ,  G11C8/10

Abstract: A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.