公开(公告)号：US20060026194A1

公开(公告)日：2006-02-02

申请号：US11176141

申请日：2005-07-06

申请人： Bharat Bhushan ,  Karlheinz Agsteiner ,  Deborah Corsi

发明人： Bharat Bhushan ,  Karlheinz Agsteiner ,  Deborah Corsi

IPC分类号： G06F7/00

CPC分类号： G06Q30/06 ,  G06F16/972

摘要： In a system and method for interacting with dynamic data, a plurality of static pages associated with corresponding products of a database may be generated, operability of a plurality of dynamic pages that is each associated with a corresponding product of the database may be maintained subsequent to the generation of the static pages, an interactive session may be established in response to a request for a dynamic page but not in response to a request for a static page, and submission of a static page to a webcrawler may be omitted without a request from the webcrawler for the static page.

摘要翻译： 在与动态数据交互的系统和方法中，可以生成与数据库的相应产品相关联的多个静态页面，每个与数据库的相应产品相关联的多个动态页面的可操作性可以在 静态页面的生成可以响应于对动态页面的请求而建立交互式会话，而不是响应于静态页面的请求，并且可以省略将静态页面提交给webcrawler而没有请求 静态页面的webcrawler。

公开(公告)号：US06813628B2

公开(公告)日：2004-11-02

申请号：US09746771

申请日：2000-12-22

申请人： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

发明人： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

IPC分类号： G06F704

CPC分类号： G06F7/5095 ,  G06F7/02 ,  G06F7/026 ,  G06F7/48 ,  G06F7/4824

摘要： A method and apparatus is disclosed to compare numbers for equality. The numbers represented in a redundant form, including numbers received from a bypass circuit are subtracted. More specifically, a complemented form is generated and supplied to an arithmetic circuit for at least one number represented in the redundant form. Input to the arithmetic circuit is adjusted to augment a result generated through the arithmetic circuit to generate a valid outcome represented in the redundant form as a result of a subtraction operation. Results of the subtraction operation are compared to zero in redundant form using a non-propagative circuit and without requiring carry propagation, thereby producing an equality comparison of the number in redundant form.

摘要翻译： 公开了一种方法和装置，用于比较相等的数字。 减去以冗余形式表示的数字，包括从旁路电路接收的数字。更具体地，产生补码形式并将其提供给用冗余形式表示的至少一个数字的运算电路。 调整运算电路的输入以增加通过算术电路产生的结果，以产生作为减法运算的结果以冗余形式表示的有效结果。 使用非传播电路将减法操作的结果与冗余形式进行比较，而不需要进位传播，从而产生冗余形式的数量的等式比较。

公开(公告)号：US06756791B1

公开(公告)日：2004-06-29

申请号：US10165497

申请日：2002-06-07

申请人： Bharat Bhushan ,  Christopher D. Hahm

发明人： Bharat Bhushan ,  Christopher D. Hahm

IPC分类号： G01R2726

CPC分类号： H02J1/10 ,  G01Q10/06 ,  G11B2005/001

摘要： The present invention includes capacitive film thickness measurement devices and measurement systems. The invention also includes machines or instruments using those aspects of the invention. The present invention additionally includes methods and procedures using those devices of the present invention. The present invention discloses a capacitance measurement device and technique useful in determining lubricant film thickness on substrates such as magnetic thin-film rigid disks. Using the present invention, variations in lubricant thickness on the Angstrom scale or less may be measured quickly and nondestructively.

摘要翻译： 本发明包括电容膜厚度测量装置和测量系统。 本发明还包括使用本发明的这些方面的机器或仪器。 本发明另外包括使用本发明的那些装置的方法和程序。 本发明公开了一种用于确定诸如磁性薄膜刚性盘的衬底上的润滑剂膜厚度的电容测量装置和技术。 使用本发明，可以快速且非破坏性地测量润滑剂厚度在埃刻度或更小的变化。

公开(公告)号：US06191618B1

公开(公告)日：2001-02-20

申请号：US09360110

申请日：1999-07-23

申请人： Eric Gayles ,  Bharat Bhushan ,  Debashree Ghosh

发明人： Eric Gayles ,  Bharat Bhushan ,  Debashree Ghosh

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output of the first domino gate. A first input of a reset gate is coupled to the output of the first domino gate, with a second input of the reset gate being coupled to the output of the second domino gate. The reset gate outputs a precharge signal coupled to a second input of the second domino gate when the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.

摘要翻译： 多米诺骨牌逻辑电路包括：第一多米诺牌，其响应于时钟信号，复位门和第二多米诺牌，评估一个或多个输入，其具有耦合到第一多米诺式门的输出的第一输入。 复位门的第一输入端耦合到第一多米诺门的输出，复位门的第二输入耦合到第二多米诺门的输出端。 当第二多米诺式门被放电并且第一多米诺式门的输出改变状态时，复位门输出耦合到第二多米诺门的第二输入的预充电信号，使得在第一输入端发生高到低的转换 第二个多米诺骨牌门

公开(公告)号：US5558903A

公开(公告)日：1996-09-24

申请号：US326345

申请日：1994-10-20

申请人： Bharat Bhushan ,  James V. Coe, Jr. ,  Balkishan Gupta

发明人： Bharat Bhushan ,  James V. Coe, Jr. ,  Balkishan Gupta

IPC分类号： C23C14/06 ,  C01B31/02

CPC分类号： C23C14/0605 ,  Y10S423/39 ,  Y10S423/40 ,  Y10S427/102 ,  Y10T428/30

摘要： The invention relates to an improved synthesis of fullerene (C.sub.60) films, whereby improved purity and adhesion to a substrate are achieved. The invention is not limited to C.sub.60 molecules and other fullerenes and fullerene based materials, including for example, metallofullerenes, fluorinated fullerenes, and codeposition of fullerene and other solid lubricants. The invention also relates to the use of these fullerene materials in oils, greases, polymers and other materials, both organic and inorganic, for improving lubrication and wear life. The invention further relates to a process for the ion bombardment of fullerene materials, including but not limited to, C.sub.60 fullerene materials to improve their tribological properties.

摘要翻译： 本发明涉及富勒烯（C60）膜的改进合成，从而实现了提高的纯度和对基材的粘合性。 本发明不限于C60分子和其它富勒烯和富勒烯基材料，包括例如金属富勒烯，氟化富勒烯，以及富勒烯和其它固体润滑剂的共沉积。 本发明还涉及这些富勒烯材料在油，油脂，聚合物和其它有机和无机材料中的用途，以改善润滑和磨损寿命。 本发明还涉及用于离子轰击富勒烯材料的方法，包括但不限于C60富勒烯材料以改善其摩擦学性能。

公开(公告)号：US5523723A

公开(公告)日：1996-06-04

申请号：US443131

申请日：1995-05-17

申请人： Christopher G. Arcus ,  Bharat Bhushan ,  Paul D. Ta

发明人： Christopher G. Arcus ,  Bharat Bhushan ,  Paul D. Ta

IPC分类号： H03K3/0231 ,  H03K3/03 ,  H03L7/099 ,  H03B5/04

CPC分类号： H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

摘要： A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.

摘要翻译： 锁相环电路的环形多级VCO包括两个或更多个差分放大器级。 锁相环包括连接在控制电压端子和电压 - 电流转换器级之间的低通滤波器，其包括具有源电阻器R1的第一源极跟随器MOS晶体管M1和与其连接的二极管连接的MOS晶体管M2 漏极端子。 电流源MOS晶体管M8具有连接到第一MOS晶体管M1的漏极的栅极端子，使得晶体管M8镜像晶体管M1的电流。 二极管连接的晶体管M9的栅极端子和其漏极端子连接在一起，并且还连接到晶体管M8的漏极端子。 差分放大器级包括电流源MOS晶体管M10，其电流源MOS晶体管M10的栅极端子连接到第一MOS晶体管M1的漏极，以电流镜像M1的漏极电流。 差分放大器级还包括连接到电流源MOS晶体管M10的漏极端子的一对MOS晶体管M4和M5。 MOS晶体管M4的栅极端子为IN端子，MOS晶体管M5的栅极端子为IN端子。 MOS晶体管M4的漏极端子为差分放大器级提供OUT信号，MOS晶体管M5的漏极端为差分放大器级提供OUT信号。 MOS晶体管M6形成MOS晶体管M4的负载阻抗，MOS晶体管M7形成MOS晶体管M5的负载阻抗。 M6和M7的栅极端子连接到晶体管M9的漏极端子。

公开(公告)号：US4227756A

公开(公告)日：1980-10-14

申请号：US974264

申请日：1978-12-29

申请人： Bharat Bhushan

发明人： Bharat Bhushan

IPC分类号： F16C17/12 ,  F16C33/12 ,  F16C33/16 ,  F16C17/00 ,  F16C33/00

CPC分类号： F16C17/024 ,  F16C33/16 ,  F16C2360/23 ,  F16C33/1095 ,  Y10S384/913

摘要： A high temperature, low friction, flexible coating for metal surfaces which are subject to rubbing contact includes a mixture of three parts graphite and one part cadmium oxide, ball milled in water for four hours, then mixed with thirty percent by weight of sodium silicate in water solution and a few drops of wetting agent. The mixture is sprayed 12-15 microns thick onto an electro-etched metal surface and air dried for thirty minutes, then baked for two hours at 65.degree. C. to remove the water and wetting agent, and baked for an additional eight hours at about 150.degree. C. to produce the optimum bond with the metal surface. The coating is afterwards burnished to a thickness of about 7-10 microns.

摘要翻译： 经受摩擦接触的金属表面的高温，低摩擦，柔性涂层包括三部分石墨和一部分氧化镉的混合物，在水中球磨4小时，然后与30重量％的硅酸钠混合 水溶液和几滴润湿剂。 将混合物12-15微米厚喷涂到电蚀刻的金属表面上并空气干燥30分钟，然后在65℃下烘烤2小时以除去水和润湿剂，并在约 150℃，以产生与金属表面的最佳结合。 之后将涂层抛光至约7-10微米的厚度。

公开(公告)号：US20160274936A1

公开(公告)日：2016-09-22

申请号：US14660905

申请日：2015-03-17

申请人： VAKUL GARG ,  Bharat Bhushan ,  Ruchika Gupta

发明人： VAKUL GARG ,  Bharat Bhushan ,  Ruchika Gupta

IPC分类号： G06F9/48 ,  G06F9/46

CPC分类号： G06F9/4881 ,  G06F9/466 ,  G06F9/52

摘要： A data processing system includes a host processor, a co-processor, and a memory that includes multiple buffer descriptor (BD) rings. The host processor includes multiple cores that execute multiple threads to process data packets stored in the memory. The host processor generates a notification command based on multiple context switch events that occur in the cores. The notification command indicates a context switch event type and BD ring IDs associated with BD rings to be polled by the co-processor. The BD rings are referred to as active BD rings. The co-processor polls only the active BD rings based on the notification command and processes the data packets associated with the active BD rings.

摘要翻译： 数据处理系统包括主处理器，协处理器和包括多个缓冲器描述符（BD）环的存储器。 主处理器包括执行多个线程以处理存储在存储器中的数据分组的多个核。 主机处理器基于核心中发生的多个上下文切换事件来生成通知命令。 通知命令指示与协处理器轮询的BD环相关联的上下文切换事件类型和BD环ID。 BD环被称为活动BD环。 协处理器仅基于通知命令轮询主动BD环，并处理与活动BD环相关联的数据包。

公开(公告)号：US09396154B2

公开(公告)日：2016-07-19

申请号：US14258046

申请日：2014-04-22

申请人： Vakul Garg ,  Bharat Bhushan

发明人： Vakul Garg ,  Bharat Bhushan

IPC分类号： G06F13/24 ,  G06F13/42 ,  G06F13/40 ,  H04L12/883

CPC分类号： G06F13/4221 ,  G06F13/24 ,  G06F13/4068 ,  H04L49/9021 ,  H04L63/0485

摘要： A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively.

摘要翻译： 用于管理数据包的系统具有多个核心，数据缓冲器，硬件加​​速器和中断控制器。 中断控制器基于从硬件加速器接收到的第一硬件信号将第一中断信号发送到第一核心。 第一核心创建与第一虚拟队列中的数据缓冲器中的数据分组相对应的缓冲器描述符环的缓冲器描述符（BD）的副本，并向硬件加速器指示数据分组被处理。 如果存在额外的数据分组，则中断控制器将第二中断信号发送到第二核心，其执行与由第一核心执行的步骤相同的步骤。 第一和第二核心分别同时处理与第一和第二虚拟队列中的BD相关联的数据分组。

公开(公告)号：US20110177288A1

公开(公告)日：2011-07-21

申请号：US13078296

申请日：2011-04-01

申请人： Bharat Bhushan ,  Yong Chae Jung ,  Michael Nosonovsky

发明人： Bharat Bhushan ,  Yong Chae Jung ,  Michael Nosonovsky

IPC分类号： B32B3/00 ,  B05D1/38

CPC分类号： B32B27/08 ,  B05D1/60 ,  B05D5/08 ,  B05D7/02 ,  B08B17/06 ,  B08B17/065 ,  B32B27/06 ,  B32B27/283 ,  B32B27/38 ,  B32B2307/73 ,  Y10T428/24355 ,  Y10T428/24479 ,  Y10T428/24612 ,  Y10T428/24802

摘要： Embodiments of methods of making superhydrophobic structures comprise depositing a polymer mold onto a silicon surface comprising a plurality of microasperities, removing the polymer mold after the polymer mold has hardened, depositing a liquid epoxy resin into the polymer mold, forming a microstructure with a plurality of microasperities by separating the epoxy resin from the mold after the epoxy resin has solidified, and forming a superhydrophobic structure by depositing a plurality of alkane nanoasperities on the microstructure in the presence of solvent vapor.

摘要翻译： 制造超疏水结构的方法的实施方案包括将聚合物模具沉积到包含多个微结构的硅表面上，在聚合物模具硬化后去除聚合物模具，将液体环氧树脂沉积到聚合物模具中，形成具有多个 通过在环氧树脂固化之后将环氧树脂与模具分离，并通过在溶剂蒸气存在下在微结构上沉积多个烷烃纳米级，形成超疏水结构，从而形成微孔。