公开(公告)号：US20230418792A1

公开(公告)日：2023-12-28

申请号：US17851546

申请日：2022-06-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Annmary Justine KOOMTHANAM ,  Suparna Bhattacharya ,  Aalap Tripathy ,  Sergey Serebryakov ,  Martin Foltin ,  Paolo Faraboschi

IPC: G06F16/215 ,  G06F16/25 ,  G06F16/27 ,  G06N20/00 ,  G06K9/62

CPC classification number: G06F16/215 ,  G06F16/254 ,  G06F16/27 ,  G06N20/00 ,  G06K9/6256

Abstract: Systems and methods are provide for automatically constructing data lineage representations for distributed data processing pipelines. These data lineage representations (which are constructed and stored in a central repository shared by the multiple data processing sites) can be used to among other things, clone the distributed data processing pipeline for quality assurance or debugging purposes. Examples of the presently disclosed technology are able to construct data lineage representations for distributed data processing pipelines by (1) generating a hash content value for universally identifying each data artifact of the distributed data processing pipeline across the multiple processing stages/processing sites of the distributed data processing pipeline; and (2) creating an data processing pipeline abstraction hierarchy for associating each data artifact to input and output events for given executions of given data processing stages (performed by the multiple data processing sites).

公开(公告)号：US20210225440A1

公开(公告)日：2021-07-22

申请号：US17223435

申请日：2021-04-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06N3/04 ,  G11C29/52 ,  G06F11/10

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

公开(公告)号：US10984860B2

公开(公告)日：2021-04-20

申请号：US16364717

申请日：2019-03-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06F11/10 ,  G06N3/04 ,  G11C29/52

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

公开(公告)号：US10671291B2

公开(公告)日：2020-06-02

申请号：US15770753

申请日：2015-11-17

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B Lesartre ,  Martin Foltin

IPC: G06F3/06 ,  G06F13/24 ,  G06F13/16

Abstract: Example implementations relate to memory read requests. For example, an implementation may include tracking progress of an iterative write sequence to write data to a memory element of a memory module. A received read request is detected to be addressed to a memory bank that includes the memory element undergoing the iterative write sequence. Based on the tracked progress, a time is determined to interrupt the iterative write sequence with insertion of the read request. The time aligns between operations of the iterative write sequence and data is returned within a predetermined read latency.

公开(公告)号：US10460800B2

公开(公告)日：2019-10-29

申请号：US15748667

申请日：2015-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B Lesartre ,  Martin Foltin ,  Yoocharn Jeon

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4074

Abstract: A data storage device includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.

公开(公告)号：US10452472B1

公开(公告)日：2019-10-22

申请号：US15997030

申请日：2018-06-04

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Catherine Graves ,  John Paul Strachan ,  Dejan S. Milojicic ,  Paolo Faraboschi ,  Martin Foltin ,  Sergey Serebryakov

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09 ,  H03M13/35

Abstract: A dot-product engine (DPE) implemented on an integrated circuit as a crossbar array (CA) includes memory elements comprising a memristor and a transistor in series. A crossbar with N rows, M columns may have N×M memory elements. A vector input for N voltage inputs to the CA and a vector output for M voltage outputs from the CA. An analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC) may be coupled to each input/output register. Values representing a first matrix may be stored in the CA. Voltages/currents representing a second matrix may be applied to the crossbar. Ohm's Law and Kirchoff's Law may be used to determine values representing the dot-product as read from the crossbar. A portion of the crossbar may perform Error-correcting Codes (ECC) concurrently with calculating the dot-product results. ECC codes may be used to only indicate detection of errors, or for both detection and correction of results.

公开(公告)号：US10318205B2

公开(公告)日：2019-06-11

申请号：US15113901

申请日：2014-01-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Martin Foltin

IPC: G06F3/06 ,  G06F12/08 ,  G06F11/14 ,  G06F12/0868

Abstract: A method for managing data using a number of non-volatile memory arrays is described. The method includes writing data from a volatile memory region to a first non-volatile memory array. The method also includes writing a remaining portion of the data from the volatile memory region to a second non-volatile memory array in response to detecting that an event has occurred. The second non-volatile memory array has a lower write latency than the first non-volatile memory array.

公开(公告)号：US20170308296A1

公开(公告)日：2017-10-26

申请号：US15136827

申请日：2016-04-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Gregg B. Lesartre ,  Martin Foltin

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685

Abstract: In various examples, a memory may comprise a first subarray having an associated first staging buffer, a second subarray having an associated second staging buffer, and request logic. The request logic may: receive a first write request associated with the first subarray, receive a second write request associated with the second subarray, store the first write request in the first staging buffer, store the second write request in the second staging buffer, and execute the first write request and the second write request.

公开(公告)号：US09773547B2

公开(公告)日：2017-09-26

申请号：US15113914

申请日：2014-01-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Richard H. Henze ,  Naveen Muralimanohar ,  Yoocharn Jeon ,  Martin Foltin ,  Erik Ordentlich ,  Gregg B. Lesartre ,  R. Stanley Williams

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C5/02 ,  H01L23/528

CPC classification number: G11C13/004 ,  G11C5/025 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79 ,  H01L23/528 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

公开(公告)号：US09767901B1

公开(公告)日：2017-09-19

申请号：US15245607

申请日：2016-08-24

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  Gary Gibson ,  Naveen Muralimanohar ,  Martin Foltin ,  Greg Astfalk

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

Abstract: An integrated circuit is provided. In an example, the integrated circuit includes a first address line, a selector device electrically coupled to the first address lines, and a memory device electrically coupled between the selector device and a second address line. The selector device has a first I-V response in a first current direction and a second I-V response in a second current direction that is different from the first I-V response.