公开(公告)号：US20050057556A1

公开(公告)日：2005-03-17

申请号：US10949990

申请日：2004-09-23

申请人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

发明人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/021 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28

摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.

摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

公开(公告)号：US20050008753A1

公开(公告)日：2005-01-13

申请号：US10496984

申请日：2002-11-19

申请人： Takeshi Honda ,  Takeshi Imazawa ,  Yasushi Kubota ,  Tadashi Nakatsubo

发明人： Takeshi Honda ,  Takeshi Imazawa ,  Yasushi Kubota ,  Tadashi Nakatsubo

IPC分类号： A23C9/152 ,  A23F3/16 ,  A23F3/18 ,  A23F5/24 ,  A23F5/26 ,  A23G1/00 ,  A23G1/30 ,  A23L1/221 ,  A23L1/30 ,  A23L2/02 ,  A23L2/04 ,  A23L2/38 ,  C12C1/00

CPC分类号： A23L2/04 ,  A23F3/18 ,  A23F5/26 ,  A23F5/265 ,  A23F5/267 ,  A23L2/38 ,  A23L27/10 ,  A23L27/11 ,  A23L33/105

摘要： A food objective for extraction and/or squeezing is charged into a colloid mill or a twin-screw extruder; immediately after and/or while milling, a low-temperature solvent (for example, water or milk of from −3 to 50° C.) is added; and after treating the food using the extruder, grounds are removed to produce an extract and/or a squeezed liquid. After milling objective foods, for example, a single product or a combination of foods such as coffee, green tea, black tea, herb tea, wild grass tea, Chinese medical tea, cocoa, vanilla, fruit, and vegetable, extraction and/or squeezing can be rapidly and extremely efficiently carried out at a low temperature, which is appropriate for the mass and continuous production. Furthermore, in comparison with the conventional employed extraction and/or squeezing methods such as a low-temperature extraction method which leads to deterioration in flavor due to oxidation after milling, etc. and requires a long time, the present invention brings effects extremely advantageous from the viewpoints of enhancement of flavor and economy. For example, in tea based drinks, a useful component suspends, whereby a vivid color tone inherent to each tea is kept over a long time.

摘要翻译： 将用于萃取和/或挤压的食品物料装入胶体磨或双螺杆挤出机中; 在研磨之后和/或碾磨时，加入低温溶剂（例如，水或牛奶-3至50℃）; 并且在使用挤出机处理食物之后，除去土壤以产生提取物和/或挤压液体。 在研磨客观食物之后，例如，单一产品或咖啡，绿茶，红茶，草本茶，野草，中医茶，可可，香草，水果和蔬菜等食品的组合，提取和/或 可以在适合于质量和连续生产的低温下快速且极其有效地进行挤压。 此外，与常规使用的提取和/或挤压方法相比，例如导致由于碾磨后的氧化导致的风味劣化等而需要较长时间的低温提取方法，本发明带来了非常有益的效果 增强风味和经济性的观点。 例如，在茶基饮料中，有用的成分悬浮，由此可以长时间保持每种茶固有的生动色调。

公开(公告)号：US06724361B1

公开(公告)日：2004-04-20

申请号：US09703918

申请日：2000-11-01

申请人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

发明人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

IPC分类号： G09G336

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/0289

摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. An output pulse having the same width as the pulse of the clock signal is generated.

摘要翻译： 在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。 时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。 产生具有与时钟信号的脉冲相同宽度的输出脉冲。

公开(公告)号：US06603455B1

公开(公告)日：2003-08-05

申请号：US09176193

申请日：1998-10-21

申请人： Hongyong Zhang ,  Yosuke Tsukamoto ,  Yutaka Takafuji ,  Yasushi Kubota

发明人： Hongyong Zhang ,  Yosuke Tsukamoto ,  Yutaka Takafuji ,  Yasushi Kubota

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G3/3677

摘要： A display panel drive circuit and a display panel are provided which are simple in structure but free from initial failure leading to impossibility to perform scanning. The display panel drive circuit of the present invention is structured such that thin film transistors constituting a signal input circuit connected to a circuit outside the display panel are formed in a structure having a dielectric breakdown strength higher than those of thin film transistors constituting other circuits. Specifically, countermeasures are taken by transistor formation in multi-gate structure, gate width broadening, resistance insertion between an input terminal and a transistor or the like. In the present invention, the circuit to which signals are externally inputted or thin film transistors of the same circuit is structured to withstand high voltage, thereby preventing the transistors from being deteriorated by high voltage and occurrence of initial failure while being simple in structure.

摘要翻译： 提供了一种显示面板驱动电路和显示面板，其结构简单，但没有初始故障，导致不可能执行扫描。 本发明的显示面板驱动电路被构造成使得构成与显示面板外部的电路连接的信号输入电路的薄膜晶体管形成为具有高于构成其它电路的薄膜晶体管的介电击穿强度的结构。 具体地，通过多栅极结构中的晶体管形成，栅极宽度加宽，输入端子和晶体管之间的电阻插入等来采取对策。 在本发明中，外部输入信号的电路或同一电路的薄膜晶体管被构造为承受高电压，从而防止晶体管在结构简单的同时由于高电压和初始故障的发生而劣化。

公开(公告)号：US06556162B2

公开(公告)日：2003-04-29

申请号：US09847661

申请日：2001-05-02

申请人： Michael James Brownlow ,  Graham Andrew Cairns ,  Catherine Rosinda Marie Armida Dachs ,  Hidehiko Yamashita ,  Yasushi Kubota ,  Hajime Washio

发明人： Michael James Brownlow ,  Graham Andrew Cairns ,  Catherine Rosinda Marie Armida Dachs ,  Hidehiko Yamashita ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： H03M166

CPC分类号： H03M1/682 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2310/027 ,  H03M1/687 ,  H03M1/765 ,  H03M1/804

摘要： A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.

摘要翻译： 数模转换器包括第一转换器级1，用于通过选择合适的低阻抗参考电压将k位输入信号的m个最高有效位转换为上限和下限电压极限VL和VH。 第二转换器级2在由电压限制VL和VH限定的电压范围内执行k位输入的n个最低有效位的线性转换。 包括开关SW1和SW2的预充电电路从负载CLOAD断开级2，负载CLOAD在预充电阶段期间被充电到电压极限VL。 负载随后与电压限制VL断开并连接到级2的输出，以完成负载CLOAD到转换器输出电压的充电。

公开(公告)号：US06492972B1

公开(公告)日：2002-12-10

申请号：US09275261

申请日：1999-03-23

申请人： Yasushi Kubota ,  Tamotsu Sakai ,  Hajime Washio

发明人： Yasushi Kubota ,  Tamotsu Sakai ,  Hajime Washio

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G2300/0408 ,  G09G2320/0209

摘要： A data signal line driving circuit which sequentially forms a plurality of sampling signals and continuously samples input signals to output such input signals, in response to the plurality of sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.

摘要翻译： 数据信号线驱动电路，响应于多个采样信号顺次形成多个采样信号并连续采样输入信号以输出这些输入信号，其中采样信号分别表示彼此不同的采样周期， 并且将每个采样信号的脉冲宽度规定为较小，使得每个采样信号的上升和下降彼此不重叠。

公开(公告)号：US06476637B1

公开(公告)日：2002-11-05

申请号：US09568892

申请日：2000-05-11

申请人： Michael James Brownlow ,  Graham Andrew Cairns ,  Yasushi Kubota ,  Hajime Washio

发明人： Michael James Brownlow ,  Graham Andrew Cairns ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： H03K190175

CPC分类号： H03K3/356113

摘要： A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.

摘要翻译： 电压电平移位器包括交叉耦合源跟随器形式的输入级和放大器AMP形式的输出级，其可以具有单端或差分输入。 源极跟随器包括晶体管M1和M2以及晶体管M3和M4。 差分输入IN和！IN连接到晶体管M2和M4的栅极。 从晶体管M3的漏极和晶体管M4的源极连接的节点B向晶体管M1的栅极提供偏置电压。 类似地，偏置电压从晶体管M1的漏极和晶体管M2的源极连接到的节点A提供给晶体管M3的栅极。

公开(公告)号：US06465806B2

公开(公告)日：2002-10-15

申请号：US09095587

申请日：1998-06-11

申请人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai ,  Zhang Hongyong ,  Jun Koyama

发明人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai ,  Zhang Hongyong ,  Jun Koyama

IPC分类号： H01L2904

CPC分类号： H01L23/5226 ,  G02F1/1345 ,  G02F1/13454 ,  G09G3/3688 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first conductive layer; an interlayer insulative layer having an opening; and a second conductive layer. The first conductive layer, the interlayer insulative layer and the second conductive layer are sequentially laminated. The opening is partially covered by the second conductive layer, and an area of the first conductive layer is substantially entirely covered by the second conductive layer in the opening.

摘要翻译： 半导体器件包括第一导电层; 具有开口的层间绝缘层; 和第二导电层。 第一导电层，层间绝缘层和第二导电层依次层叠。 开口部分被第二导电层覆盖，并且第一导电层的面积基本上完全被开口中的第二导电层覆盖。

公开(公告)号：US06373460B1

公开(公告)日：2002-04-16

申请号：US09684912

申请日：2000-10-10

申请人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

发明人： Yasushi Kubota ,  Ichiro Shiraki ,  Tamotsu Sakai

IPC分类号： G09G336

CPC分类号： G09G3/3674 ,  G09G3/20 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2310/06 ,  H01L27/12 ,  H01L29/78

摘要： A matrix-type image display device of the present invention is arranged such that image data are selectively applied to pixels arranged in a matrix form through scanning signal lines and data signal lines, and the image data are stored therein, wherein a high potential of a sampling pulse 0V/5V to be output from a logic circuit is shifted to 10 V, and a low potential thereof is shifted to −8 V respectively by first and second level shifters. As a result, a difference between an input signal level from an external circuit such as a control circuit, an image signal processing circuit, etc., and an actual driving signal level of each pixel can be absorbed. Therefore, an additional structure such as an interface circuit, etc., is not needed between the external circuit and the scanning signal line driving circuit, thereby enabling a low cost and a low power consumption.

摘要翻译： 本发明的矩阵型图像显示装置被布置成使得图像数据被选择性地施加到通过扫描信号线和数据信号线以矩阵形式布置的像素，并且图像数据被存储在其中，其中高电位 从逻辑电路输出的采样脉冲0V / 5V被移位到10V，并且其低电位分别由第一和第二电平移位器移位到-8V。 结果，可以吸收来自诸如控制电路的外部电路的输入信号电平，图像信号处理电路等之间的差异和每个像素的实际驱动信号电平之间的差异。 因此，在外部电路和扫描信号线驱动电路之间不需要诸如接口电路等的附加结构，从而能够实现低成本和低功耗。

公开(公告)号：US06262598B1

公开(公告)日：2001-07-17

申请号：US09517984

申请日：2000-03-03

申请人： Graham Andrew Cairns ,  Michael James Brownlow ,  Yasushi Kubota ,  Hajime Washio

发明人： Graham Andrew Cairns ,  Michael James Brownlow ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： H03K190175

CPC分类号： G11C7/062 ,  H03K19/018521 ,  H03K19/018528 ,  H03K19/01855

摘要： A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gate of the transistor T1 is connected to a direct signal input IN whereas the gate of the transistor T2 receives a shifted version of the direct input signal from a source-follower comprising the transistors T3 and T4. The level shifter may also be embodied as a differential cross-coupled sense amplifier with the sources of the drain load transistors being crossed coupled to the differential inputs.

摘要翻译： 电压电平移位器包括连接在电源线vdd和反相输入端IN之间的互补晶体管T1，T2。 晶体管T1的栅极连接到直接信号输入IN，而晶体管T2的栅极接收来自包括晶体管T3和T4的源极跟随器的直接输入信号的偏移版本。 电平移位器还可以被实现为差分交叉耦合读出放大器，其中漏极负载晶体管的源极与差分输入交叉耦合。