公开(公告)号：US06414883B2

公开(公告)日：2002-07-02

申请号：US09860795

申请日：2001-05-21

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：USRE36089E

公开(公告)日：1999-02-09

申请号：US652008

申请日：1996-05-23

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US5321657A

公开(公告)日：1994-06-14

申请号：US865145

申请日：1992-04-08

申请人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

发明人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1048

摘要： In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

摘要翻译： 在CSL系统的动态RAM中，存储器阵列被分成多个存储器阵列部分，并且设置在各个存储器阵列部分中的位线对响应于CSL输出而同时连接到它们对应的I / O线对 。 在这样的RAM中，只有要访问的存储器阵列部分的I / O线对被预充电到VCC-Vth的电平，而不存储阵列部分的I / O线对被预充电到 1 / 2xVCC的电平与位线对相同。 这使得可以实现更快的数据读取操作，并且还防止不必要的电流在未加工的存储器阵列部分中的位线对和I / O线对之间流动。

公开(公告)号：US4809230A

公开(公告)日：1989-02-28

申请号：US938065

申请日：1986-12-04

申请人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

发明人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

IPC分类号： G11C11/407 ,  G11C11/34 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/00 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/4076 ,  G11C11/4094

摘要： A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

摘要翻译： MOS动态型RAM包括存储单元（10），虚设单元（11），位线对（BL，＆amp; B和B），字线（WL），虚拟字线（DWL）和读出放大器（12）。 在非有效周期中，每对位线（BL，＆amp; B和B）的电位在电源电位VCC的1/2处被预充电。 每个读出放大器（12）在非活动周期之后的有效周期中工作，而每个有源上拉电路（13）将该对位线中较高一级的电位上拉至VCC。 该活动周期由内部RAS内部信号定义，该内部RAS内部信号由NAND电路（27）响应于通过延迟电路（20）延迟外部＆upbar＆R信号而获得的外部＆upbar＆R信号和＆upbar＆R信号产生的内部RAS内部信号， 并且具有通过将外部＆upbar＆R信号的后沿延迟预定周期而获得的后沿。

公开(公告)号：US4757476A

公开(公告)日：1988-07-12

申请号：US876912

申请日：1986-06-20

申请人： Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

发明人： Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

IPC分类号： G11C11/401 ,  G11C7/14 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4099 ,  G11C7/02

CPC分类号： G11C7/14 ,  G11C11/4099

摘要： A dummy word line driving circuit for a MOS dynamic RAM comprises a dummy word line controller connected to each end of a pair of dummy word lines. A sub-decode signal which is opposite to the one inputted to a dummy word driver and a dummy set signal for writing a bit line information into a not-selected dummy cell are inputted to the dummy word line controller. Means for applying a dummy equalizing signal is connected to two full-sized dummy cells, for equalizing the two before the dummy word line is driven. The two full-sized dummy cells are equalized by the signal, resulting in a charge amount, which is to be a reference value, of a half of a full-sized memory cell.

摘要翻译： 用于MOS动态RAM的虚拟字线驱动电路包括连接到一对虚拟字线的每一端的虚拟字线控制器。 将与输入到虚拟字驱动器的子解码信号相反的子解码信号和用于将位线信息写入未选择的虚拟单元的伪设置信号被输入到虚拟字线控制器。 用于应用虚拟均衡信号的装置连接到两个全尺寸的虚拟小区，用于在虚拟字线被驱动之前均衡两者。 两个全尺寸虚拟单元被信号相等，导致作为参考值的充电量为全尺寸存储单元的一半。

公开(公告)号：US4722074A

公开(公告)日：1988-01-26

申请号：US774358

申请日：1985-09-10

申请人： Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

发明人： Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Tsutomu Yoshihara

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C11/4076 ,  G11C11/4096 ,  G11C7/1048

摘要： A first precharging and equalizing circuit (7) precharges and equalizes I/O buses (10 and 10') in advance to selection of bit lines, and following thereto, a second precharging and equalizing circuit (12) precharges and equalizes the I/O buses (10 and 10') during driving operation of a sense amplifier (2). Thus, potential levels of the I/O Buses (10 and 10') are prevented from being changed by vibration of the output level of the sense amplifier (2) transmitted to the I/O buses (10 and 10') through parasitic capacitance (8) during driving operation of the sense amplifier (2).

摘要翻译： 第一预充电均衡电路（7）预先对I / O总线（10和10'）进行预充电和均衡，以选择位线，之后，第二预充电均衡电路（12）预充电并使I / O均衡 在读出放大器（2）的驱动操作期间，总线（10和10'）。 因此，防止I / O总线（10和10'）的电位电平被通过寄生电容传输到I / O总线（10和10'）的读出放大器（2）的输出电平的振动而改变 （8）在读出放大器（2）的驱动操作期间。

公开(公告)号：US4712123A

公开(公告)日：1987-12-08

申请号：US771023

申请日：1985-08-30

申请人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Tsutomu Yoshihara ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka

发明人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Tsutomu Yoshihara ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka

IPC分类号： G11C11/404 ,  G11C11/4074 ,  G11C11/413 ,  H01L29/78

CPC分类号： G11C11/4074

摘要： A dynamic memory device including 1-transistor, 1-capacitor type dynamic memory cell, wherein a half voltage of the writing voltage is applied to a cell plate, and a constant voltage is applied to the substrate.

摘要翻译： 一种包括1-晶体管，1-电容器型动态存储单元的动态存储器件，其中写入电压的一半电压被施加到单元板，并且将恒定电压施加到衬底。

公开(公告)号：US5315548A

公开(公告)日：1994-05-24

申请号：US900368

申请日：1992-06-18

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US4896297A

公开(公告)日：1990-01-23

申请号：US112034

申请日：1987-10-23

申请人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

发明人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC分类号： G11C8/08

CPC分类号： G11C8/08

摘要： A circuit for generating a boosted signal for a word line, coupled to a word line driving signal line for transmitting a voltage signal to the word line, coupled to a first power supply, and coupled to a second power supply for providing a voltage higher than the voltage of the first power supply, can supply a compensating voltage for the word line from the second power supply through the word line driving signal line when a voltage of the word line is decreased.

摘要翻译： 一种用于产生用于字线的升压信号的电路，耦合到字线驱动信号线，用于将电压信号传输到字线，耦合到第一电源，并耦合到第二电源，以提供高于 当字线的电压减小时，第一电源的电压可以通过字线驱动信号线从第二电源提供用于字线的补偿电压。

公开(公告)号：US4835743A

公开(公告)日：1989-05-30

申请号：US92615

申请日：1987-09-03

申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Kazutoshi Hirayama

发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Kazutoshi Hirayama

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/409

CPC分类号： G11C7/1033

摘要： In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of a nibble mode, so that the time period required for reading out data in the nibble mode is reduced as compared with a conventional device.

摘要翻译： 在能够进行半字节模式操作的半导体存储器件中，从正常模式时和在上一时刻起，当＆amp; C＆gt;信号下降到数据输出缓冲器激活信号上升时的时间所需的时间段变得不同 半字节模式，因此与常规设备相比，读取半字节模式中的数据所需的时间段被减少。