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    Self-refresh control circuit and semiconductor memory device including the same
    31.
    发明授权
    Self-refresh control circuit and semiconductor memory device including the same 有权
    自刷新控制电路和包括其的半导体存储器件

    公开(公告)号：US07649797B2

    公开(公告)日：2010-01-19

    申请号：US12031110

    申请日：2008-02-14

    Applicant: Soo-Man Hwang ,  Ho-Cheol Lee

    Inventor： Soo-Man Hwang ,  Ho-Cheol Lee

    IPC: G11C7/22

    CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4087 ,  G11C2211/4065 ,  G11C2211/4068

    Abstract: A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage.

    Abstract translation: 半导体存储器件中的刷新控制电路包括刷新控制器，电压发生器和字线使能电路。 刷新周期控制器响应于自刷新信号产生控制信号，该控制信号指示刷新周期的标称启动。 电压发生器响应于控制信号产生输出电压。 在刷新期间，输出电压从低电压升压到高电压。 字线使能电路响应于控制信号产生字线使能信号，其中在刷新周期的标称启动之后的延迟之后，字线使能信号被激活，并且延迟允许电压发生器完全提升输出 电压。

    Multiprocessor system and method thereof
    32.
    发明申请
    Multiprocessor system and method thereof 有权
    多处理器系统及其方法

    公开(公告)号：US20080172516A1

    公开(公告)日：2008-07-17

    申请号：US11819601

    申请日：2007-06-28

    Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    IPC: G06F12/02

    CPC classification number: G06F12/02

    Abstract: A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

    Abstract translation: 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为银行地址作为银行地址，选择第三个存储器 银行通过第一个港口。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR
    33.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR 失效
    半导体存储器件及其方法

    公开(公告)号：US20070171755A1

    公开(公告)日：2007-07-26

    申请号：US11616846

    申请日：2006-12-27

    Applicant: Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    Inventor： Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C11/406 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618

    Abstract: A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.

    Abstract translation: 提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。 在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域 多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。 授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

    Semiconductor package having multiple embedded chips
    34.
    发明授权
    Semiconductor package having multiple embedded chips 有权
    具有多个嵌入式芯片的半导体封装

    公开(公告)号：US07170157B2

    公开(公告)日：2007-01-30

    申请号：US10803043

    申请日：2004-03-18

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: H01L23/02 ,  H01L23/34

    CPC classification number: H01L25/065 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014

    Abstract: A semiconductor package includes multiple embedded chips, each chip including a common circuit having substantially the same common function. The common circuit in a selected one of the chips is enabled. The common circuit in one or more other ones of the chips is disabled. As a result, the enabled common circuit performs the common function for the selected chip and the one or more other chips.

    Abstract translation: 半导体封装包括多个嵌入式芯片，每个芯片包括具有基本上相同的共同功能的公共电路。 所选择的一个芯片中的公共电路被使能。 一个或多个其他芯片中的公共电路被禁用。 结果，使能的公共电路执行所选择的芯片和一个或多个其他芯片的共同功能。

    Multi-bank dynamic random access memory devices having all bank precharge capability
    37.
    发明授权
    Multi-bank dynamic random access memory devices having all bank precharge capability 有权
    具有全部预充电能力的多组动态随机存取存储器件

    公开(公告)号：US06343036B1

    公开(公告)日：2002-01-29

    申请号：US09157271

    申请日：1998-09-18

    Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC: G11C700

    CPC classification number: G11C7/1018 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于 灭活信号在预充电循环中工作。

    Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
    38.
    发明授权
    Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation 有权
    利用时钟屏蔽信号来控制内部时钟信号产生的同步动态随机存取存储器件

    公开(公告)号：US06279116B1

    公开(公告)日：2001-08-21

    申请号：US09390220

    申请日：1999-09-03

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: G06F114

    CPC classification number: G11C7/225 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Method controlling deep power down mode in multi-port semiconductor memory
    40.
    发明授权
    Method controlling deep power down mode in multi-port semiconductor memory 有权
    在多端口半导体存储器中控制深度掉电模式的方法

    公开(公告)号：US08391095B2

    公开(公告)日：2013-03-05

    申请号：US12768060

    申请日：2010-04-27

    Applicant: Ho-Cheol Lee ,  Jung-Bae Lee

    Inventor： Ho-Cheol Lee ,  Jung-Bae Lee

    IPC: G11C5/14

    CPC classification number: G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

    Abstract: Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

    Abstract translation: 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

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