公开(公告)号：US20120145446A1

公开(公告)日：2012-06-14

申请号：US13210392

申请日：2011-08-16

申请人： Jie YANG ,  Qingchin He ,  Hanmin Zhang

发明人： Jie YANG ,  Qingchin He ,  Hanmin Zhang

IPC分类号： H05K1/02 ,  H01L21/28

CPC分类号： H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48992 ,  H01L2224/85138 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/20753 ,  H01L2224/85399

摘要： An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

摘要翻译： 电连接包括结合到靠近模具边缘的相邻接合焊盘的第一引线和第二引线，其中一端接合到芯片边缘远离管芯接合焊盘，第二端接合引线框架的引线指 或基板的连接垫。 第二根线穿过并被第一根线支撑。 第一线作为防止第二线接触芯片边缘的支架。 第一根线也防止了第二根线在封装期间过度的横向运动。

公开(公告)号：US06975020B2

公开(公告)日：2005-12-13

申请号：US10750942

申请日：2004-01-05

申请人： Ho-Cheol Lee

发明人： Ho-Cheol Lee

IPC分类号： H01L21/60 ,  H01L23/50 ,  H01L23/495 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48 ,  H01L2224/4811 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2224/45099

摘要： A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.

摘要翻译： 一种半导体集成电路器件，包括具有由外围电路区域包围的存储单元阵列区域的半导体芯片，并且包括仅在该半导体芯片的一侧上至少一排设置的多个焊盘。 电路装置可以包括邻近焊盘侧设置的第一引线组和与第一引线组相对设置的第二引线组。 第二引线组可以形成在半导体芯片的一部分上（片上芯片结构）。 多个接合线分别将第一和第二引线组与多个接合焊盘连接。

公开(公告)号：US20190198374A1

公开(公告)日：2019-06-27

申请号：US16293099

申请日：2019-03-05

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Darrell D. TRUHITTE ,  James P. LETTERMAN, JR.

IPC分类号： H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11418 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27418 ,  H01L2224/2746 ,  H01L2224/27462 ,  H01L2224/276 ,  H01L2224/279 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75755 ,  H01L2224/75756 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81856 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83856 ,  H01L2224/85005 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92147 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207

摘要： Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

公开(公告)号：US09984994B2

公开(公告)日：2018-05-29

申请号：US15432559

申请日：2017-02-14

申请人： The Charles Stark Draper Laboratory, Inc.

发明人： Tirunelveli Sriram ,  Brian Smith ,  Bryan Mclaughlin ,  John Lachapelle

IPC分类号： H01K3/10 ,  H01L23/00 ,  H01L23/13 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  A61N1/05 ,  A61B5/04 ,  A61N1/375

CPC分类号： H01L24/83 ,  A61B5/0031 ,  A61B5/04001 ,  A61N1/05 ,  A61N1/0543 ,  A61N1/0551 ,  A61N1/375 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/45169 ,  H01L2224/4811 ,  H01L2224/48496 ,  H01L2224/83007 ,  H01L2224/83345 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83986 ,  H01L2224/85 ,  H01L2224/85007 ,  H01L2224/85345 ,  H01L2224/85385 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/0001 ,  H01L2224/05599

摘要： A method for bonding a hermetic module to an electrode array including the steps of: providing the electrode array having a flexible substrate with a top surface and a bottom surface and including a plurality of pads in the top surface of the substrate; attaching the hermetic module to the bottom surface of the electrode array, the hermetic module having a plurality of bond-pads wherein each bond-pad is adjacent to the bottom surface of the electrode array and aligns with a respective pad; drill holes through each pad to the corresponding bond-pad; filling each hole with biocompatible conductive ink; forming a rivet on the biocompatible conductive ink over each pad; and overmolding the electrode array with a moisture barrier material.

公开(公告)号：US20170236790A1

公开(公告)日：2017-08-17

申请号：US15043080

申请日：2016-02-12

申请人： Semtech Corporation

发明人： Satyamoorthi Chinnusamy ,  Weng Hing Tan ,  Jayson Nathaniel S. Reyes

IPC分类号： H01L23/66 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/66 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/642 ,  H01L23/645 ,  H01L23/647 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/6661 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49052 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/45099

摘要： A semiconductor device includes a substrate and a first conductive layer formed over a first surface of the substrate. The first conductive layer is patterned into a first portion of a first passive circuit element. The first conductive layer is patterned to include a first coiled portion. A second conductive layer is formed over a second surface of the substrate. The second conductive layer is patterned into a second portion of the first passive circuit element. The second conductive layer is patterned to include a second coiled portion exhibiting mutual inductance with the first coiled portion. A conductive via formed through the substrate is coupled between the first conductive layer and second conductive layer. A semiconductor component is disposed over the substrate and electrically coupled to the first passive circuit element. An encapsulant is deposited over the semiconductor component and substrate. The substrate is mounted to a printed circuit board.

公开(公告)号：US09583458B2

公开(公告)日：2017-02-28

申请号：US13836582

申请日：2013-03-15

申请人： The Charles Stark Draper Laboratory, Inc.

发明人： Tirunelveli Sriram ,  Brian Smith ,  Bryan Mclaughlin ,  John Lachapelle

IPC分类号： H01K3/10 ,  H01L23/00 ,  A61N1/375 ,  A61B5/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  A61B5/04 ,  A61N1/05 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L24/83 ,  A61B5/0031 ,  A61B5/04001 ,  A61N1/05 ,  A61N1/0543 ,  A61N1/0551 ,  A61N1/375 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/45169 ,  H01L2224/4811 ,  H01L2224/48496 ,  H01L2224/83007 ,  H01L2224/83345 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83986 ,  H01L2224/85 ,  H01L2224/85007 ,  H01L2224/85345 ,  H01L2224/85385 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/0001 ,  H01L2224/05599

摘要： A method for bonding a hermetic module to an electrode array including the steps of: providing the electrode array having a flexible substrate with a top surface and a bottom surface and including a plurality of pads in the top surface of the substrate; attaching the hermetic module to the bottom surface of the electrode array, the hermetic module having a plurality of bond-pads wherein each bond-pad is adjacent to the bottom surface of the electrode array and aligns with a respective pad; drill holes through each pad to the corresponding bond-pad; filling each hole with biocompatible conductive ink; forming a rivet on the biocompatible conductive ink over each pad; and overmolding the electrode array with a moisture barrier material.

摘要翻译： 一种将密封模块粘合到电极阵列的方法，包括以下步骤：提供具有顶表面和底表面的柔性基底的电极阵列，并且在基底的顶表面中包括多个垫片; 将密封模块附接到电极阵列的底表面，密封模块具有多个接合焊盘，其中每个接合焊盘邻近电极阵列的底表面并与相应的焊盘对齐; 通过每个焊盘钻孔到相应的焊盘; 用生物相容的导电油墨填充每个孔; 在每个垫上的生物相容性导电油墨上形成铆钉; 并用防潮材料包覆模制电极阵列。

公开(公告)号：US20120175755A1

公开(公告)日：2012-07-12

申请号：US13005279

申请日：2011-01-12

申请人： Reinhold Bayerer

发明人： Reinhold Bayerer

IPC分类号： H01L23/34 ,  H01L21/50

CPC分类号： H01L24/29 ,  H01L23/051 ,  H01L23/057 ,  H01L23/24 ,  H01L23/36 ,  H01L23/373 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05693 ,  H01L2224/06181 ,  H01L2224/27505 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29298 ,  H01L2224/32113 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48177 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48639 ,  H01L2224/48647 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48839 ,  H01L2224/48847 ,  H01L2224/48893 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/8384 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/48793 ,  H01L2224/48693 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/83205

摘要： A semiconductor device includes a semiconductor chip including back side metal, a substrate, and an electrically conductive heat spreader directly contacting the back side metal. The semiconductor chip includes a sintered joint directly contacting the heat spreader and electrically coupling the heat spreader to the substrate.

摘要翻译： 半导体器件包括半导体芯片，其包括背面金属，基板和直接接触背面金属的导电散热器。 半导体芯片包括直接接触散热器并将散热器电耦合到基板的烧结接头。

公开(公告)号：US20040164422A1

公开(公告)日：2004-08-26

申请号：US10750942

申请日：2004-01-05

发明人： Ho-Cheol Lee

IPC分类号： H01L023/48

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48 ,  H01L2224/4811 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2224/45099

摘要： A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.

摘要翻译： 一种半导体集成电路器件，包括具有由外围电路区域包围的存储单元阵列区域的半导体芯片，并且包括仅在该半导体芯片的一侧上至少一排设置的多个焊盘。 电路装置可以包括邻近焊盘侧设置的第一引线组和与第一引线组相对设置的第二引线组。 第二引线组可以形成在半导体芯片的一部分上（片上芯片结构）。 多个接合线分别将第一和第二引线组与多个接合焊盘连接。

公开(公告)号：US20180174881A1

公开(公告)日：2018-06-21

申请号：US15883625

申请日：2018-01-30

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Darrell D. TRUHITTE ,  James P. LETTERMAN, JR.

IPC分类号： H01L21/683 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/495 ,  H01L23/36 ,  H01L21/78

CPC分类号： H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11418 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/27418 ,  H01L2224/2746 ,  H01L2224/27462 ,  H01L2224/276 ,  H01L2224/279 ,  H01L2224/2908 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4811 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75755 ,  H01L2224/75756 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81856 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83856 ,  H01L2224/85005 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92147 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207

摘要： Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

公开(公告)号：US20150162269A1

公开(公告)日：2015-06-11

申请号：US14098560

申请日：2013-12-06

申请人： Wai Yew Lo

发明人： Wai Yew Lo

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/50 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/4811 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4917 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/0665 ,  H01L2924/00012

摘要： A semiconductor die package has a die mounted to a die pad. The die has data bond pads and power supply bond pads. Lead fingers are spaced from and project outwardly from the die pad. Each of the lead fingers has a proximal end that is near to a respective edge of the die pad, and a distal end farther from the die pad. The lead fingers include power bar lead fingers and data lead fingers. A power bar bridges the proximal ends of two of the power bar lead fingers. The power bar is between the proximal ends of the data lead fingers and the respective edge of the die pad. Insulated bond wires are used to selectively electrically couple the power bar to the die power supply bond pads.

摘要翻译： 半导体管芯封装具有安装到管芯焊盘的管芯。 芯片具有数据接合焊盘和电源接合焊盘。 引导指与管芯焊盘间隔开并向外突出。 每个引线指具有靠近芯片焊盘的相应边缘的近端，以及远离管芯焊盘的远端。 引导指包括电源条引线指和数据引线指。 电源杆桥接两根电源线引脚的近端。 电源杆位于数据引线指的近端和芯片焊盘的相应边缘之间。 绝缘接合线用于选择性地将功率条电耦合到芯片电源接合焊盘。